• 한국세라믹학회지
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• 제53권2호
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• pp.150-161
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• 2016

The conventional brick-layer model is not satisfactory either in theory or in practice for the description of dispersive responses of polycrystalline solid electrolytes with current-constriction effects at the grain boundaries. Parallel networks of complex dielectric functions have been shown to successfully describe the AC responses of polycrystalline sodium conductors over a wide temperature and frequency range using only around ten model parameters of well-defined physical significance. The approach can be generally applied to many solid electrolyte systems. The present work illustrates the approach by simulation. Problems of bricklayer model analysis are demonstrated by fitting analysis of the simulated data under experimental conditions.

• 한국표면공학회지
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• 제43권1호
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• Journal of Korean Vacuum Science & Technology
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• 제4권3호
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• pp.73-77
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• 2000

Single crystal and polycrystalline Si thin films were doped with phosphorus by a 2-zone diffusion method to develop the low-resistivity polycrystalline Si electrode for a hemispherical grain. Solid phosphorus source was used in order to achieve uniformly and highly doped surface region of polycrystalline Si films having rough surface morphology. In case of 2-zone diffusion method, it is proved that the heavy doping near the surface area can be achieved even at a relatively low temperature. SIMS analysis revealed that phosphorus doping concentration in case of using solid P as a doping source was about 50 times as that of phosphine source at 750$^{\circ}C$. Also, ASR analysis revealed that the carrier concentration was about 50 times as that of phosphine. In order to evaluate the electrical characteristics of doped polycrystalline Si films for semiconductor devices, MOS capacitors were fabricated to measure capacitance of polycrystalline Si films. In ${\pm}$2 V measuring condition, Si films, doped with solid source, have 8% higher $C_{min}$ than that of unadditional doped Si films and 3% higher $C_{min}$ than that of Si films doped with $PH_3$ source. The leakage current of these films was a few fA/${\mu}m^2$. As a result, a 2-zone diffusion method is suggested as an effective method to achieve highly doped polycrystalline Si films even at low temperature.

• 대한기계학회논문집A
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• 제21권8호
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• pp.1291-1297
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• 1997

Elastic-plastic finite element(FE) simulation was performed for polycrystalline solids subjected to plane strain tensile loading. Using Asaro's double slip crystal plasticity model, the polycrystalline solids were modeled by assigning different initial slip directions to each grain. From the FE calculations, the microscopic deformation characteristics of polycrystalline solids were analyzed. Moreover, the effect of grain size and grain boundaries on the deformation characteristics were clarified.

• The Korean Journal of Ceramics
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• 제4권2호
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• pp.122-127
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• 1998

Conductivities of polycrystalline ceria doped with several rare earth oxides were measured by AC admittance and DC four probe method. The conductions were separated into grain and grain boundary contributions using the complex admittance technique as well as grain size dependence of conductivity. The grain size dependence of polycrystalline conductivity, which can be adequately described by the so-called brick layer model, appears to give a more reliable measure of the grain conductivity compared to the complex admittance method. Polycrystalline resistivity(1/conductivity) increases linearly with the reciprocal of grain size. The intercept of resistivity vs. inverse grain size plot gives a measure of the grain resistivity and the slope gives a measure of the grain boundary resistivity. It was also noted that errors involved in the analysis of experimental data may be different between the complex admittance method and the impedance method. A greater resolution of the spectra was found in the complex admittance method, insofar as the present work is concerned, suggesting that the commonly used equivalent circuit may require re-evaluation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.322-325
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• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.129-134
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• 2004

The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1994년도 추계 학술발표 강연 및 논문 개요집
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• pp.33-33
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• 1994

• 한국방재학회 논문집
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• 제11권2호
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• pp.39-44
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• 2011

마이크로 스케일에서 다결정 재료의 소성 거동을 살펴볼 때, 결정의 geometrically necessary dislocation(GND) 효과에 의한 소성 구배(plastic gradient)를 고려하는 것은 재료의 소성 거동에 큰 영향을 줄 수 있다. 이러한 영향을 확인하기 위하여, 본 연구에서는 소성 구배의 영향을 고려한 다결정 고체(polycrystalline solids)의 거동을 유한요소해석을 이용하여 살펴보았다. 소성 구배의 영향을 살펴보기 위해 구배 경화 계수(gradient hardness coefficient)와 먼 거리 변형률에 대한 재료 길이 변수 (material length parameter)가 사용되었다. 재료 길이 변수에 의한 영향을 확인하기 위해, 재료 길이 변수의 차이에 따른 다결정 고체의 거동을 분석하였다. 또한 소성 구배 효과의 고려 및 재료 길이 변수에 따른 다결정 고체 내부에 위치한 단결정이 받는 영향을 살펴보았다. 재료 길이 변수에 따라 결정이 받는 영향을 비교하여, GND에 의한 다결정 고체 거동의 영향을 확인하였다.