• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• 한국세라믹학회지
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• 제52권1호
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• pp.72-76
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• 2015

150-nm-thick In-Zn-Tin-Oxide (IZTO) films were deposited by RF magnetron sputtering after a 10 to 50-nm-thick $SiO_2$ buffer layer was deposited by plasma enhanced chemical vapor deposition (PECVD) on polyethylene terephthalate (PET) substrates. The electrical, structural, and optical properties of the IZTO/$SiO_2$/PET films were analyzed with respect to the thickness of the $SiO_2$ buffer layer. The mechanical properties were outstanding at a $SiO_2$ thickness of 50 nm, with a resistivity of $1.45{\times}10^{-3}{\Omega}-cm$, carrier concentration of $8.84{\times}10^{20}/cm^3$, hall mobility of $4.88cm^2/Vs$, and average IZTO surface roughness of 12.64 nm. Also, the transmittances were higher than 80%, and the structure of the IZTO films were amorphous, regardless of the $SiO_2$ thickness. These results indicate that these films are suitable for use as a transparent conductive oxide for transparency display devices.

• 반도체디스플레이기술학회지
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• 제11권2호
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• pp.13-16
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• 2012

Zinc oxide (ZnO) films were deposited by an RF magnetron sputtering system with the RF power of 200W and 300W and flow rate of oxygen gases of 20 and 30 sccm, in order to research the growth of ZnO on carbon doped silicon oxide (SiOC) thin film. The reflectance of SiOC film on Si film deposited by the sputtering decreased with increasing the oxygen flow rate in the range of long wavelength. In comparison between ZnO/Si and ZnO/SiOC/Si thin film, the reflectance of ZnO/SiOC/Si film was inversed that of ZnO/Si film in the rage of 200~1000 nm. The transmittance of ZnO film increased with increasing the oxygen gas flow rate because of the transition from conduction band to oxygen interstitial band due to the oxygen interstitial (Oi) sites. The low reflectance and the high transmittance of ZnO film was suitable properties to use for the front electrode in the display or solar cell.

• 전자공학회논문지D
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• 제35D권12호
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• pp.68-74
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• 1998

본 논문에서는 electron cyclotron resonance (ECR) N₂O-플라즈마 산화막을 게이트 산화막으로 사용한 다결정 실리콘 박막 트랜지스터 (TFT)의 성능과 단채널 특성에 대하여 연구하였다. ECR NE₂O-플라즈마 게이트 산화막을 사용한 소자는 열산화막을 이용한 경우에 비해 우수한 성능과 억제된 단채널 효과를 나타낸다. 얇은 ECR N2O-플라즈마 산화막을 사용하여 n채널 TFT의 경우 3 ㎛, p채널 TFT의 경우 1㎛ 게이트 길이까지 문턱 전압 감소가 없는 소자를 얻었다. 이러한 특성 향상은 부드러운 계면, passivation 효과, 그리고 계면과 박막 내부에 존재하는 강한 Si ≡ N 결합 등에 기인한다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• 전기전자학회논문지
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• 제18권4호
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• pp.447-455
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• 2014

본 연구에서는 4H-SiC MOSFET의 주요 문제점인 $SiC/SiO_2$ 계면의 특성을 향상시키기 위해 PECVD (plasma enhanced chemical vapor deposition) 공정을 이용하여 n-based 4H-SiC MOS Capacitor를 제작하였다. 건식 산화 공정의 낮은 성장속도, 높은 계면포획 밀도와 $SiO_2$의 낮은 항복전계 등의 문제를 극복하기 위하여 PECVD와 NO어닐링 공정을 사용하여 MOS Capacitor를 제작하였다. 제작이 끝난 후, MOS Capacitor의 계면특성을 hi-lo C-V 측정, I-V 측정 및 SIMS를 이용해 측정하고 평가하였다. 계면의 특성을 건식 산화의 경우와 비교한 결과 20% 감소한 평탄대 전압 변화, 25% 감소한 $SiO_2$ 유효 전하 밀도, 8MV/cm의 증가한 $SiO_2$ 항복전계 및 1.57eV의 유효 에너지 장벽 높이, 전도대 아래로 0.375~0.495eV만큼 떨어져 있는 에너지 영역에서 69.05% 감소한 계면 포획 농도를 확인함으로써 향상된 계면 및 산화막 특성을 얻을 수 있었다.

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2000년도 춘계총회,특별강연,심포지움,연구발표회
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• pp.62.2-62.2
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• 2000

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• 센서학회지
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• 제9권5호
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• pp.389-395
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• 2000

본 논문에서는 보호용 실리콘 산화층과 Al 층을 이용한 $Al_2O_3$ 예비층의 형성을 제안하였다. 실리콘 기판 위의 보호용 산화막 위에 알루미늄을 증착하고 이를 $800^{\circ}C$에서 열처리함으로써 에피텍시 $Al_2O_3$ 예비층 형성시킬 수 있었다. 그리고 형성된 $Al_2O_3$ 예비층위에 ${\gamma}-Al_2O_3$ 층을 형성하였다. ${\gamma}-Al_2O_3$막 성장시 공정의 초기 상태에서 발생하는 $N_2O$ 가스에 의한 Si 기판의 식각을 $Al_2O_3$ 예비층을 이용함으로써 방지할 수 있었다. $Al_2O_3$ 예비층이 초박막 ${\gamma}-Al_2O_3$의 표면의 형태를 개선하는데 많은 효과가 있었다.

• Bulletin of the Korean Chemical Society
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• 제17권7호
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• pp.621-625
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• 1996

A variety of metal oxides were coated by sol-gel process from their metal alkoxides on the ribbons of Co-based and Fe-based amorphous alloys, and the effects of surface oxide coating on the magnetic properties of the alloy are investigated. The core loss is found to be reduced significantly by the oxide coating, the loss reduction becoming more prominent at higher frequencies. The shape of the hystersis loop is also dependent upon the kind of the coated metal oxide. The coatings of MgO, SiO2, MgO·SiO2 and MgO·Al2O3 induce tensile stress into the Fe-based ribbon whereas those of BaO, Al2O3, CaO·Al2O3, SrO·Al2O3 and BaO·Al2O3 induce compressive stress. These results may be explained by the modification of domain structures via magnetoelastic interactions with the shrinkage stress induced by the sol-gel coating.