• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.81-82
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• 2006

SOI(Silicon-On-Insulator) MOSFET의 전기적 특성에 미치는 게이트 산화막과 계면준위 밀도의 관계를 조사하였다. 결함이 발생하지 않는 얕은 소스/드레인 접합을 형성하기 위하여 급속열처리를 이용한 고상확산방법으로 제작한 SOI MOSFET 소자는 급속열처리 과정에서 계면준위가 증가하여 소자의 특성이 열화된다. 이를 개선하기 위하여 $H_2/N_2$ 분위기에서 후속 열처리 공정을 함으로써 소자의 특성이 향상됨을 볼 수 있었다. 이와같이 급속열처리 공정과 $H_2/H_2$ 분위기에서의 후속 열처리 공정이 소자 특성에 미치는 영향을 분석하기 위하여 소자 시뮬레이션을 이용하여 게이트 산화막과 채널 사이의 계면준위 밀도를 분석하였다. 그 결과, n-MOSFET의 경우에는 acceptor-type trap, p-MOSFET의 경우에는 donor-type trap density가 소자특성에 큰 영향을 미치는 것을 확인하였다.

• 전력전자학회논문지
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• 제25권3호
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• pp.204-212
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• 2020

In this study, device suitability analysis is performed by comparing the performance of SiC MOSFET and GaN Transistor, which are WBG power semiconductor devices in the induction heating (IH) system. WBG devices have the advantages of low conduction resistance, switching losses, and fast switching due to their excellent physical properties, which can achieve high output power and efficiency in IH systems. In this study, SiC and GaN are applied to a general half-bridge series resonant converter topology to compare the conduction loss, switching loss, reverse conduction loss, and thermal performance of the device in consideration of device characteristics and circuit conditions. On this basis, device suitability in the IH system is analyzed. A half-bridge series resonant converter prototype using the SiC and GaN of a 650-V rating is constructed to verify device suitability through performance comparison and verified through an experimental comparison of power loss and thermal performance.

• E2M - 전기 전자와 첨단 소재
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• 제9권8호
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• pp.799-805
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• 1996

In short channel MOSFET, it is very important to establish optimal process conditions because of variation of device characteristics due to the process parameters. In this paper, we used process simulator and device characteristics caused by process parameter variation. From this simulation, it has been ' derived to the dependence relations between process parameters and device characteristics. The experimental result of fabricated short channel device according to the optimal process parameters demonstrate good device characteristics.

• 대한전자공학회논문지
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• 제24권3호
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• pp.472-477
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• 1987

In order to prevent the short-channel effects due to threshold voltage adjustment implantation in conventional n+ doped silicon gate process, a new approach involving automatic doping of polycide by boron during source and drain implantation is introduced. P-MOSFET devece fabricated by theis approach shows improved short channel characteristics than conventional device with n+ doped gate. Some concerns of adopting this approach in CMOS technology are addressed togetheer with some suggestions.

• 한국전기전자재료학회논문지
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• 제27권8호
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• 한국세라믹학회지
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• 제38권10호
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• 센서학회지
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• 제27권3호
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• 대한전자공학회논문지SD
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• 제37권12호
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• pp.1-9
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• 2000

미세구조 N-채널 MOSFET의 게이트-소스 전압에 의존하는 유효 채널 캐리어 이동도와 소스 및 드레인 기생저항의 정확한 분리 추출을 위해서 새로운 ERM-방법을 제안하였다. ERM-방법은 선형영역에서 동작하는 게이트 길이가 다른 두개의 소자($W_m/L_m=30{\mu}m/0.6{\mu}m, 30{\mu}m/1{mu}m$)에 적용되었고 유효 채널 캐리어 이동도를 모델링하고 추출하는 과정에서 게이트-소스 전압에 의존하는 소스 및 드레인 기생저항의 영향을 고려하였다. ERM-방법으로 추출된 특성변수들을 사용한 해석적 모델식과 소자의 측정데이터를 비교해본 결과 오차가 거의 없이 일치하는 것을 확인하였다. 따라서, ERM-방법을 사용하면 대칭구조 및 비대칭구조 소자의 유효 채널 캐리어 이동도, 소스 및 드레인 기생저항과 다른 특성변수들을 정확하고 효율적으로 추출할 수 있을 것으로 기대된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.17-18
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• 2006

고상 확산 방법을 이용하여 얕은 소스/드레인 접합을 가지는 SOI (Silicon-On-Insulator) MOSFET 소자를 제작하였다. 확산원으로는 PSG(Phosphorus silicate glass) 박막과 PBF(Poly Boron Film) 박막이 각각 n, p-type 소자 형성을 위해 사용되었다. 얕은 접합 형성을 위하여 급속 열처리 방법(RTA: Rapid Thermal Annealing)을 이용하여 PSG와 PBF로부터 인과 붕소를 SOI MOSFET 소자의 소스/드레인으로 확산시켰다. 또한, 소자 특성 개선을 위한 후 속 열처리 공정으로 희석된 수소 분위기 중에서 FA(Furnace Annealing)를 실시하였다. SPD 기술을 적용하여 10 nm 이하의 매우 얕은 p-n 접합을 형성할 수 있었고, 양호한 다이오드 특성을 얻을 수 있었다. 또한, SPD 방법으로 결함이 없는 접합 형성이 가능하며, 소자 제작 공정의 최적화를 통해 차세대 CMOS 소자로 기대되는 SOI MOSFET를 성공적으로 제작할 수 있었다.