• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.880-886
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• 2009

Recently, the memory is used in many electronic devices, thus, the many researchers make a study of the memory. To increase a storage capacity per memory block, the researchers study for reducing the fabrication process of memory and multi-level cell memory which is storing more than 2-bits in a cell. However, the multi-level cell memory has low bit-error rates by various noises. In this paper, we study the noise of multi-level cell memory, and we propose the channel model of multi-level cell memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.706-711
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• 2012

Multi-level cell NAND flash is a flash memory technology using multiple levels per cell to allow more bits to be stored. Currently, most multi-level cell NAND stores 2 bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. The most error cause is coupling noise. Thus, in this paper, we studied coupling noise cancellation scheme for reduction memory on the 16-level cell NAND flash memory channel. Also, we compared the performance threshold detection and proposed scheme.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.8
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.25-32
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• 2011

We have analyzed adjacent cell dependency of threshold voltage shift caused by the cell to cell interference, and we proposed a 3-adjacent-cell model to model the pattern dependency of the threshold voltage shift. The proposed algorithm is verified by using MATLAB simulation and measurement results. In the experimental results, we found that accuracy of the proposed simple 3-adjacient-cell model is comparable to the widely used conventional 8-adjacient-cell model. The Bit Error Rate (BER) of LSB and of MSB is improved by 28.9% and 19.8%, respectively, by applying the proposed algorithm based on 3-adjacent-cell model to 20nm-class 2-bit MLC NAND flash memories.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.73-77
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• 2023

In this study, we developed a Multi-level FeRAM (Ferroelectrics random access memory) device utilizing different ferroelectric materials and analyzed its operation through C-V analysis using simulations. To achieve Multi-level operation, we proposed an MFM (Multi-Ferroelectric Material) structure by depositing two different ferroelectric materials with distinct properties horizontally on the same bottom electrode and subsequently adding a gate electrode on top. By analyzing C-V peaks based on the polarization phenomenon occurring under different voltage conditions for the two materials, we confirmed the feasibility of achieving Multi-level operation, where either one or both of the materials can be polarized. Furthermore, we validated the process for implementing the proposed structure using semiconductor fabrication through process simulations. These results signify the significance of the new structure as it allows storing multiple states in a single memory cell, thereby greatly enhancing memory integration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.56-56
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• 2009

In this study, we fabricated the engineered $SiO_2/Si_3N_4/SiO_2$(ONO) tunnel barrier with high-k $HfO_2$ trapping layer for application high performance flash MLC(Multi Level Cell). As a result, memory device show low operation voltage and stable memory characteristics with large memory window. Therefore, the engineered tunnel barrier with ONO stacks were useful structure would be effective method for high-integrated MLC memory applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.1-7
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• 2010

In this paper, we use the maximum-likelihood detection by the estimation of trellis targets on the 16-level cell NAND flash memory. This mechanism has a performance gain by using a maximum-likelihood detector. The NAND flash memory channel is a memory channel because of the coupling effect. Thus, we use the known data arrays to finding the targets of trellis. The maximum-likelihood detection by proposed scheme performs better than the threshold detection on the 16-level cell NAND flash memory channel.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.46-53
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• 2011

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. The CCI is a critical factor which affects occurring data errors in a cell, when surrounding cells are programed. We derived a characteristic equation for CCI considering write procedure of data that is similar with signal equalizing. The model considers the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. We verify the proposed equalizer comparing with the measured data of 1-block MLC NAND flash memory. As the simulation result, the equalizer shows an error correction ratio about 60% under 20nm NAND process.