Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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엔지니어 터널베리어($SiO_2/Si_3N_4/SiO_2$)와 고유전율($HfO_2$) 트랩층 구조를 가지는 비휘발성 메모리의 멀터레벨에 관한 연구

  • Published : 2009.11.12
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Abstract

In this study, we fabricated the engineered $SiO_2/Si_3N_4/SiO_2$(ONO) tunnel barrier with high-k $HfO_2$ trapping layer for application high performance flash MLC(Multi Level Cell). As a result, memory device show low operation voltage and stable memory characteristics with large memory window. Therefore, the engineered tunnel barrier with ONO stacks were useful structure would be effective method for high-integrated MLC memory applications.

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