• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.192-198
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• 2017

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

• Journal of Electrical Engineering and Technology
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• 제3권4호
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• pp.566-570
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• 2008

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• 센서학회지
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• 제28권5호
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• pp.329-333
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• 2019

Solution-processed oxide thin-film transistors (TFTs) have garnered great attention, owing to their many advantages, such as low-cost, large area available for fabrication, mechanical flexibility, and optical transparency. Negative bias stress (NBS)-induced instability of sol-gel IGZO TFTs is one of the biggest concerns arising in practical applications. Thus, understanding the bias stress effect on the electrical properties of sol-gel IGZO TFTs and proposing an effective recovery method for negative bias stressed TFTs is required. In this study, we investigated the variation of transfer characteristics and the corresponding electrical parameters of sol-gel IGZO TFTs caused by NBS and positive bias recovery (PBR). Furthermore, we proposed an effective PBR method for the recovery of negative bias stressed sol-gel IGZO TFTs. The threshold voltage and field-effect mobility were affected by NBS and PBR, while current on/off ratio and sub-threshold swing were not significantly affected. The transfer characteristic of negative bias stressed IGZO TFTs increased in the positive direction after applying PBR with a negative drain voltage, compared to PBR with a positive drain voltage or a drain voltage of 0 V. These results are expected to contribute to the reduction of recovery time of negative bias stressed sol-gel IGZO TFTs.

• Nuclear Engineering and Technology
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• 제50권7호
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• pp.1060-1067
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• 2018

A feasibility of reusing option of spent nuclear fuel in a fusion-fission hybrid system without partitioning was checked as an alternative option of pyro-processing with critical reactor system. Neutronic study was performed with MCNP 6.1 for this option, direct reuse of spent PWR fuel (DRUP). Various options with DRUP fuel were compared with the reference design concept; transmutation purpose blanket with (U-TRU)Zr fuel loading connected with pyro-processing. Performance parameters to be compared are transmutation performance of transuranic (TRU) nuclides, required fusion power and tritium breeding ratio (TBR). When blanket part is loaded only with DRUP, initial $k_{eff}$ level becomes too low to maintain a practical subcritical system, increasing the required fusion power. In this case, production rate of TRU nuclides exceeds the incineration rate. Design optimization is done for combining DRUP fuel with (U-TRU)Zr fuel. Reactivity swing is reduced to about 2447 pcm through fissile breeding compared to (U-TRU)Zr fuel option. Therefore, a required fusion power is reduced and tritium breeding performance is improved. However, transmutation performance with TRU nuclides especially $^{241}Am$ is degraded because of softening effect of spectrum. It is known that partitioning and transmutation should be accompanied with fusion-fission hybrid system for the effective transmutation of TRU.

• 한국응용과학기술학회지
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• 제37권5호
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• pp.1190-1199
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• 2020

본 연구의 목적은 골프 입문자들을 대상으로 12주간 훈련을 통하여 수행한 스윙에서 유효타에 미치는 변인들을 분석하고, 이를 통하여 골프 입문자들의 페어웨이 안착을 위한 유효타 요인의 기초자료를 제공하고자 한다. 본 연구의 대상은 골프 경험이 없는 입문자로 대학생 20명이 연구에 참여하였다(연령: 21.35±1.69yrs, 신장: 176.75±7.99cm, 체중: 70.70±9.76kg). 모든 대상자에게 12주간 골프 지도법에 따른 프로그램을 실시하였고, 12주차에 트랙맨 4를 이용하여 골프 스윙 시 유효타에 미치는 변인들을 산출하였다. 트랙맨 자료는 클럽 변인과 볼 변인으로 구분하여 유효타에 영향을 미치는 변인을 알아보기 위하여 이분형 로지스틱 회귀분석을 실시하였다. 클럽 변인에서 높은 다이나믹로프트(p<.01)와 낮은 페이스앵글(p<.05)은 유효타에서 나타났고, 볼 변인에서 빠른 볼스피드(p<.01), 큰 스매시팩터(p<.001), 높은 런치앵글(p<.001), 많은 스핀레이트(p<.001)도 유효타에서 나타났다. 클럽 변인의 이분형 로지스틱 회귀분석 결과, 클럽스피드(p<.05)와 다이나믹로프트(p<.01)가 증가하면 유효타의 가능성이 증가하였고, 페이스앵글(p<.001)이 증가하면 유효타의 가능성이 감소하였다. 클럽 변인에서 유효타의 영향력은 다이나믹로프트, 페이스앵글, 클럽스피드 순으로 나타났다. 볼 변인에서는 런치앵글(p<.05)이 증가하면 유효타의 가능성이 증가하였고, 런치디렉션(p<.05)이 증가하면 유효타의 가능성이 감소하였다. 볼 변인에서 유효타의 영향력은 런치앵글, 런치디렉션 순으로 나타났다. 결과를 토대로 유효타의 확률을 증가시키기 위한 조건으로, 지속적인 연습을 통하여 스윙 시 높은 다이나믹로프트와 낮은 페이스앵글 구사를 통한 클럽스피드 증가가 필요하고, 이를 통하여 런치앵글 증가와 런치디렉션 감소를 통하여 유효타의 확률이 증가될 것으로 사료된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

• 한국전기전자재료학회논문지
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• 제30권1호
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• pp.54-58
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• 2017

The effect of low temperature ($250^{\circ}C$) heat treatment after electron irradiation (irradiation time = 30, 180, 300s) on the chemical bonding and electrical properties of ZnO thin films prepared using a sol-gel process were examined. XPS (X-ray photoelectron spectroscopy) analysis showed that the electron beam irradiation decreased the concentration of M-O bonding and increased the OH bonding. As a result of the electron beam irradiation, the carrier concentration of ZnO films increased. The on/off ratio was maintained at ${\sim}10^5$ and the $V_{TH}$ values shifted negatively from 11 to 1 V. As the irradiation time increased from 0 to 300s, the calculated S. S. (subthreshold swing) of ZnO TFTs increased from 1.03 to 3.69 V/decade. These values are superior when compared the sample heat-treated at $400^{\circ}C$ representing on/off ratio of ${\sim}10^2$ and S. S. value of 10.40 V/decade.

• 한국정보통신학회논문지
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• 제20권1호
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• pp.110-116
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• 2016

본 논문에서는 디지털 임피던스 보정 회로와 이퀄라이저 회로를 가진 1.2V 5Gb/s SLVS 차동 송신단을 제안한다. 제안하는 송신단은 4-위상 출력 클록을 갖는 위상 고정 루프, 4-to-1 직렬변환기, 레귤레이터, 출력 드라이버, 그리고 신호보존성을 향상하기 위한 이퀄라이저 회로를 포함한다. 또한, built-in self-test를 위해 pseudo random bit sequence 발생기를 함께 구현한다. 제안하는 SLVS 송신단은 80mV에서 500mV의 차동 출력 전압범위를 지원한다. SLVS 송신단은 1.2V의 공급전압을 가지는 65nm CMOS공정을 이용하여 구현한다. 측정된 5Gb/s SLVS 송신단의 peak-to-peak 시간 지터는 46.67ps이며, 전력소모는 1.88mW/Gb/s이다.