DOI QR코드

DOI QR Code

High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

  • Park, Kwang-Il (College of Information & Communication Engineering, Sungkyunkwan University, Memory Division, Samsung Electronics) ;
  • Koo, Ja-Hyuck (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Shin, Won-Hwa (College of Information & Communication Engineering, Sungkyunkwan University, Memory Division, Samsung Electronics) ;
  • Jun, Young-Hyun (Memory Division, Samsung Electronics) ;
  • Kong, Bai-Sun (College of Information & Communication Engineering, Sungkyunkwan University)
  • Received : 2011.08.30
  • Published : 2012.06.30

Abstract

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

Keywords

References

  1. R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, pp.490-504, Apr., 2001.
  2. K. Y. Kim, J. M. Jang, D. Y. Yun, Dong Myong Kim, and Dae Hwan Kim, "Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs," Journal of Semiconductor Technology and Science, Vol.10, No.2, pp134-142, Jun., 2010 https://doi.org/10.5573/JSTS.2010.10.2.134
  3. H. Kim, D. Kim, and Y. Eo,"Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias," Journal of Semiconductor Technology and Science, Vol.11, No.1, pp15-22, Mar., 2011 https://doi.org/10.5573/JSTS.2011.11.1.015
  4. P. Larsson-Edefors, "Investigation on maximal throughput of a CMOS repeater chain," IEEE Trans. Circuits and Systems-I, Fundamental Theory and Application, Vol.47, No.4, pp.602-606, Apr., 2000. https://doi.org/10.1109/81.841866
  5. H. B. Bakoglu, Circuits, interconnections and Packaging for VLSI. Addison-Wesley, 1990.
  6. H. B. Bakoglu and J. D. Meindl, "Optimal interconnection circuits for VLSI," Digest of Technical Papers of IEEE Solid State Circuits Conference, Vol.27, pp.164-165, Feb., 1984.
  7. V. Adler and E. G. Friedman, "Repeater design to reduce delay and power in resistive interconnect," IEEE Transactions on Circuits and Systems - II, Vol.45, No.5, pp.607-616, May, 1998. https://doi.org/10.1109/82.673643
  8. A. Nalamalpu and W. Burleson, "Repeater Insertion in deep sub-micron CMOS: Ramp-based Analytical Model and Placement Sensitivity Analysis," IEEE International Symposium on Circuits and Systems, 2000, pp.766-769.
  9. H. B. Bakoglu, "Circuits, Interconnections and Packaging for KSI,'' Addison Wesley, 1990.
  10. J. Rabaey, "Digital Integrated Circuits, A Design Perspective, "Prentice-Hall, 1996
  11. K.-I. Park, Y.-H. Jun and B.-S. Kong, "High-speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission," International Technical Conference on Circuits Systems, Computers and Communications (ITC-CSCC), 26th, pp.378-379, Jun., 2011.
  12. D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, "A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time," IEEE Int. Solid State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.314-315, 605, Feb., 2007.