• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.778-781
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• 2002

In this paper, we designed the anti-fuse program circuit, and there are an anti-fuse program/sense/latch circuit, a negative voltage generator, power-up circuit and etc. in this circuit. An output voltage of a negative voltage generator is about -4,51V. We detected certainly it regardless of simulation result power rise time or temperature change to detect the anti-fuse program state of an anti-fuse program/sense/latch circuit and were able to know what performed a steady action. And as a result of having done a simulation while will change a resistance value voluntarily in order to check an anti-fuse resistance characteristic of this circuit oneself, it recognized as a programmed anti-fuse until 23k$\Omega$, and we were able to know that this circuit was a lot of margin than general anti-fuse resistance 500$\Omega$. Therefore, the anti-fuse program circuit of this study showed that was able to apply for configuration of the programmable logic device.

• 대한전자공학회논문지SD
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• 제46권3호
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• pp.1-9
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• 2009

본 논문에서는 MOS 트랜지스터가 FN 스트레스에 의해 문턱전압이 이동하는 현상을 이용하여 비교기 회로의 옵셋을 제거하는 방법을 소개하고, 이를 비교기 회로의 성능개선에 적용해 보인 결과를 보인다. 옵셋이 성능을 저하시키는 대표적인 회로인 DRAM의 비트라인 감지증폭기에 적용하여 옵셋을 제거하는 방법을 설명하고, 테스트 회로를 제작 및 측정하는 실험을 통해서 이를 검증한다. 본 방식은 래치구조가 포함된 모든 형태의 비교기에 적용가능하며, 스트레스-패킷이라고 명명한 형태의 스트레스 바이어스 시퀀스를 통해 다양한 초기 옵셋값을 가지는 많은 숫자의 비교기가 동시에 거의 제로 옵셋으로 수렴할 수 있음을 보인다. 또한 이 방법을 비교기 회로에 적용하는데 있어서 고려해야 할 몇 가지 신뢰도 조건에 대해서도 고찰한다.

• Corrosion Science and Technology
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• 제4권5호
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• pp.211-216
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• 2005

Failure analysis of the latch ram ball and the C-ram ball with the trade name AFBMA Gr. 50 Colmonoy No. 6, has been performed to identify the root cause of the failure. The study required the extraction of the both failed and normal balls from the nuclear fuel exchanger. Microstructures of both balls were examined after polishing and etching. Breaking tests of both the ball revealed similarity in cleavage surfaces. Fracture surfaces of both failed ball and normal ball after breaking test were examined with SEM and EDX. Microstructure of the ball revealed an austenite phase with coarse Cr rich precipitate. Indented marks observed on the surface of the failed ball are believed to be produced by overloading. In the light of the afore mentioned observations and studies, the failure mechanism of the ball in nuclear fuel exchanger seem to be caused by impact or mechanical overloading on ball.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.791-794
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• 2013

본 연구에서는 초기 핵 방사선 조건에서 반도체소자의 과도응답특성을 분석하기 위한 선행연구의 일환으로 반도체 소자의 과도방사선에 의한 영향에 대한 주요원인과 반도체의 물성, 설계구조, 공정방식의 조건에 따라 소자내부에 생성되는 광전류 거동특성에 대한 정략적인 분석을 위한 시뮬레이션 분석을 수행하였으며 결과적으로 반도체소자의 설계조건과 입력되는 과도방사선의 선량율에 따른 비선형 특성을 확인하였다.

• 전기전자학회논문지
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• 제24권3호
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• pp.890-894
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• 2020

본 논문에서는 대표적인 ESD 보호소자인 LVTSCR의 구조적 변화를 통해 높은 홀딩전압 특성을 가지는 ESD 보호소자를 제안한다. 제안된 ESD 보호소자는 병렬 PNP path와 긴 N+ drift 영역을 삽입하여 기존의 LVTSCR보다 높은 홀딩전압을 가지며, 일반적인 SCR 기반 ESD보호소자의 단점인 Latch-up 면역특성을 향상시킨다. 또한 기생 BJT들의 유효 베이스 폭을 설계변수로 설정하였으며, N-Stack 기술을 적용하여 요구되는 application에 적용할 수 있도록 시놉시스사의 TCAD 시뮬레이션을 통해 제안된 ESD 보호소자의 전기적 특성을 검증하였다.

• 한국전기전자재료학회논문지
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• 제18권1호
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• pp.17-23
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• 2005

The switching characteristics of MOS-Controlled Thyristor(MCT) is studied with variation of the channel length and impurity concentration in ON and OFF FET channel. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator and PSPICE simulator are used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of channel length and impurity concentration in P and N channel. The channel length and N impurity concentration of the proposed MCT power device show the strong affect on the transient characteristics of current and power. The N channel length affects only on the OFF characteristics of power and anode current, while the N doping concentration in P channel affects on the ON and OFF characteristics.

• 한국전기전자재료학회논문지
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• 제13권4호
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• pp.273-279
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• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• 한국전기전자재료학회논문지
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• 제15권9호
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• pp.758-763
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• 2002

A new small size Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) is proposed and fabricated to improve the characteristics of device. The entire electrode of LTEIGBT is placed to trench type electrode. The LTEIGBT is designed so that the width of device is 19w. The latch-up current density of the proposed LTEIGBT is improved by 10 and 2 times with those of the conventional LIGBT and LTIGBT. The forward blocking voltage of the LTEIGBT is 130V. At the same size, those of conventional LIGBT and TIGBT are 60V and 100V, respectively. Because the electrodes of the proposed device is formed of trench type, the electric field in the device are crowded to trench oxide. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT and the conventional LIGBT are 80mA and 70mA, respectively, at the same breakdown voltage of 150V.

• 한국위성정보통신학회논문지
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• 제9권4호
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• pp.63-68
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• 2014

PPS 구조를 갖는 N형 실리콘 제어 정류기 소자에서 부분웰 구조가 정전기 보호 성능에 미치는 영향을 고찰하였다. 종래의 NSCR 표준소자는 온-상태 저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 정전기 보호소자의 필요조건을 만족시키지 못해 적용이 어려웠으나, 본 연구에서 제안하는 부분웰 구조를 갖도록 변형 설계된 NSCR-PPS 소자는 안정한 정전기보호 성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

• 한국정보전자통신기술학회논문지
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• 제12권2호
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.