Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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New Method for Elimination of Comparator Offset Using the Fowler-Nordheim Stresses

Fowler-Nordheim 스트레스에 의한 MOS 문턱전압 이동현상을 응용한 비교기 옵셋 제거방법

  • Chung, In-Young (Department of Electronics and Communications, Kwangwoon University)
  • 정인영 (광운대학교 전자통신공학과)
  • Published : 2009.03.25
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Abstract

In this paper proposed a new method which adaptively eliminates comparator offsets using the threshold voltage shift by the Fowler-Nordheim stress. The method evaluates the sign of comparator offset and gives the FN stress to the stronger MOSFETs of the comparator, leading to offset reduction. We have used an appropriate stressing operation, named 'stress-packet', in order to converge the offset value to zero. We applied the method to the latch-type comparator which is prevalently used for DRAM bitline sense amplifier, and verified through experiments that offsets of the latch-type comparators are nearly eliminated with the stress-packet operations. We also discuss about the reliability issues that must be guaranteed for field application of this method.

본 논문에서는 MOS 트랜지스터가 FN 스트레스에 의해 문턱전압이 이동하는 현상을 이용하여 비교기 회로의 옵셋을 제거하는 방법을 소개하고, 이를 비교기 회로의 성능개선에 적용해 보인 결과를 보인다. 옵셋이 성능을 저하시키는 대표적인 회로인 DRAM의 비트라인 감지증폭기에 적용하여 옵셋을 제거하는 방법을 설명하고, 테스트 회로를 제작 및 측정하는 실험을 통해서 이를 검증한다. 본 방식은 래치구조가 포함된 모든 형태의 비교기에 적용가능하며, 스트레스-패킷이라고 명명한 형태의 스트레스 바이어스 시퀀스를 통해 다양한 초기 옵셋값을 가지는 많은 숫자의 비교기가 동시에 거의 제로 옵셋으로 수렴할 수 있음을 보인다. 또한 이 방법을 비교기 회로에 적용하는데 있어서 고려해야 할 몇 가지 신뢰도 조건에 대해서도 고찰한다.

Keywords

References

  1. S. Hong, S. Kim, J.-K. Wee, and S. Lee, "Low-Voltage DRAM Sensing Scheme with Offset-Cancellation Sense Amplifier," IEEE J. of Solid-State Circuits, vol.37, no.10, pp.1356-1360, Oct. 2002 https://doi.org/10.1109/JSSC.2002.803052
  2. Y. Watanabe, N. Nakamura, and S. Watanabe, "Offset-compensating bitline sensing scheme for high-density DRAMs," IEEE J. Solid-State Circuits, vol.29, pp.9-13, Jan. 1994 https://doi.org/10.1109/4.272089
  3. B. Razavi and B. Wooley, "Design techniquies for high-speed, high-resolution comparators," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992 https://doi.org/10.1109/4.173122
  4. Y. L. Wong, M. H. Cohen, and P. A. Abshire, "A Floating-Gate Comparator with Automatic Offset Adaptation for 10-bit Data Conversion," IEEE Trans. Circuits Syst. I, Fundam Theory Appl., vol. 52, no. 7, pp. 1316-1326, Jul. 2005 https://doi.org/10.1109/TCSI.2005.851389
  5. M. S. Liang, Y. T. Yeow, C. Chang, C. Hu and R. W. Brodersen, "MOSFET Degradation Due to Stressing of Thin Oxide," in IEDM Tech. Dig. 1982, pp. 50-53
  6. B. J Fishbein and D. B. Jackson, "Performance Degradation of N-channel MOS transistors during DC and pulsed Fowler-Nordheim stress," in Proc. Int. Reliability Physics Symp., 1990, pp. 159-163 https://doi.org/10.1109/RELPHY.1990.66080
  7. R. Kraus, "Analysis and Reduction of Sense-Amplifier Offset," IEEE J. Solid-State Circuits, vol. 24, no. 4, pp.1028-1033, Aug. 1989 https://doi.org/10.1109/4.34088
  8. 김동수, 이인희, 한건희, "옵셋이 제거된 승자 독점회로," 대한전자공학회 논문지, 제 45권 SD편, 제5호, pp. 26-32, 2008
  9. Y. Fong, I. C. Chen, S. Holland, J Lee, and C. Hu, "Dynamic Stressing of Thin Oxides," in IEDM Tech Dig., 1986, pp. 664-667
  10. M. S. Liang, S. Haddad, W. Cox, and S. Cagnina, "Degradation of Very Thin Gate Oxide MOS Devices Under Dynamic High Field/Current Stress," in IEDM Tech Dig. 1986, pp. 394-398
  11. E. Rosenbaum, Z. Liu, and C. Hu, "Silicon Dioxide Breakdown Lifetime Enhancement Under Bipolar Bias Conditions," IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2287-2295, Dec. 1993 https://doi.org/10.1109/16.249477
  12. Y. Mitani, T. Yamaguchi, H. Satake, and A. Toriumi, "Reconsideration of Hydrogen Related Degradation Mechanism in Gate Oxide," in Proc. Int. Reliability Physics Symp., 2007, pp. 226-231 https://doi.org/10.1109/RELPHY.2007.369896