• Proceedings of the KIEE Conference
• /
• 1987.07a
• /
• pp.473-476
• /
• 1987

Low temperature phosphorus-nitride CVD was newly developed for a high quality gate insulator on InP substrate. This film showed the Poole-Frenkel type conduction in high electric field with resistivity higher than $1{\times}10^{14}$ ohm-cm near the electric field of $1{\times}10^7\;volt/cm$. The C-V hysteresis width was very small as 0.17 volt. The density of interface trap states was $2{\times}10^{11}cm^{-2}ev^{-1}$ below the conduction band edge of InP substrate. Effective electron mobility was about $1200-1500\;cm^2/Vsec$ and showed the instability of PN-InP MISFETs drain current reduced less than 10 percent for the period $0.5-10^3sec$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.6
• /
• pp.586-591
• /
• 2004

We studied the dependence of hot-tarrier-induced degradation characteristics on nitrogen concentration in NO(Nitrided-Oxide) gate of nMOS, under ac and dc stresses. The $\Delta$V$_{t}$ and $\Delta$G$_{m}$ dependence of nitrogen concentration were observed, We observed that device degradation was suppressed significantly when the nitrogen concentration in the gate was increased. Compared to $N_2$O oxynitride, NO oxynitride gate devices show a smaller sensitivity to ac stress frequency. Results suggest that the improved at-hot carrier immunity of the device with NO gate may be due to the significantly suppressed interface state generation and neutral trap generation during stress.ess.

• Electrical & Electronic Materials
• /
• v.3 no.3
• /
• pp.195-204
• /
• 1990

본 논문에서는 컴퓨터를 근본으로 한 Deep Level Transient Spectroscopy (DLTS) 장치를 구성하고 이를 이용하여 P형 Si MOS 캐패시터의 Si- $SiO_{2}$ 계면상태를 측정하여 트랩의 활성화에너지와 포획단면적 그리고 계면트랩밀도를 조사하였다. 실리콘 band gap내에 연속적으로 분포하고 있는 계면트랩을 상세히 고찰하기 위해 quiescent 전압의 위치를 변화시키면서 0.1volt의 미소한 펄스를 MOS에 주입하여 그 각각이 분리된 트랩이라고 생각되는 매우 좁은 에너지 영역에서 나오는 DLTS신호를 측정하였다. 또한 quiescent 전압의 위치, 주입펄스전압의 진폭 그리고 rate window의 선택이 DLTS 신호에 미치는 영향 등을 조사하였다. 측정결과, 계면트랩의 활성화에너지는 가전자대로 부터 0.16-0.45eV이고 포획단면적은 1.3*$10^{-19}$~3.2*$10^{-15}$$cm^{2}$, 계면트랩밀도는 1.8*$10^{10}$ ~ 2.5*$10^{11}$$cm^{-2}$e$V^{-1}$로 측정되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.11-12
• /
• 2007

The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.6
• /
• pp.462-465
• /
• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2000.02a
• /
• pp.26-26
• /
• 2000

High quality epitaxial Y2O3 thin films were prepared on Si(111) and (001) substaretes by using ion beam assisted deposition. As a substrate, clean and chemically oxidized Si wafers were used and the effects of surface state on the film crystallinity were investigated. The crystalline quality of the films were estimated by x-ray scattering, rutherford backscattering spectroscopy/channeling, and high-resolution transmission electron microscopy (HRTEM). The interaction between Y and Si atoms interfere the nucleation of Y2O3 at the initial growth stage, it could be suppressed by the interface SiO2 layer. Therefore, SiO2 layer of the 4-6 layers, which have been known for hindering the crystal growth, could rather enhance the nucleation of the Y2O3 , and the high quality epitaxial film could be grown successfully. Electrical properties of Y2O3 films on Si(001) were measured by C-V and I-V, which revealed that the oxide trap charge density of the film was 1.8$\times$10-8C/$\textrm{cm}^2$ and the breakdown field strength was about 10MV/cm.

• Journal of the Semiconductor & Display Technology
• /
• v.17 no.4
• /
• pp.27-31
• /
• 2018

The effect of $NH_3$ plasma passivation on the chemical and electrical characteristics of ALD HfAlO dielectric on the InGaAs substrate was investigated. The results show that $NH_3$ plasma passivation exhibit better electrical & chemical performance such as much lower leakage current, lower density of interface trap(Dit) level, and low unstable interfacial oxide. $NH_3$ plasma passivation can effectively enhance interfacial characteristics. Therefore $NH_3$ plasma passivation improved the HfAlO dielectric performance on the InGaAs substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.11a
• /
• pp.163-166
• /
• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.4
• /
• pp.198-202
• /
• 2018

In this work, we have investigated the effect of a 30-min thermal anneal at $550^{\circ}C$ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.2 no.1
• /
• pp.3-9
• /
• 2009

Although Active matrix organic light emitting diode (AMOLED) display has a better image quality in terms of viewing angle, contrast ratio, and response time than liquid crystal displays (LCDs), it still has some critical issues such as lifetime, residual images, and brightness non-uniformity due to non-uniformity in electrical characteristics of driving TFTs and IR drops on supplied power line. Among them, we improved irrecoverable residual images of AMOLED displays which is mainly related to the hysteresis characteristics of driving TFTs. We consider four kinds of surface treatment conditions before gate oxide deposition for improving hysteresis characteristics. We can reduce the hysteresis level of p-channel TFT to 0.23 V, interface trap states between the poly-Si layer and gate insulator to $3.11{\times}10^{11}cm^{-2}$, and output current variation of p-channel TFT to 3.65 % through the surface treatment using ultraviolet light and H2 plasma. Therefore, the recoverable residual image problem of AMOLED displays can be improved by surface treatment using ultraviolet light and $H_2$ plasma.