Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)
- 2007.11a
- /
- Pages.11-12
- /
- 2007
Evaluation of nano-sSOI wafer using pseudo-MOSFET
Pseudo-MOSFET을 이용한 nano-sSOI 기판의 특성 평가
- Jung, Myung-Ho (Department of Electronic materials engineering, Kwangwon Univ.) ;
- Kim, Kwan-Su (Department of Electronic materials engineering, Kwangwon Univ.) ;
- Choi, Chel-Jong (Nano-Bio Electronic Devices Team, Electronics and Telecommunications Research Institute) ;
- Cho, Won-Ju (Department of Electronic materials engineering, Kwangwon Univ.)
- Published : 2007.11.01
Abstract
The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.