• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.956-958
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• 1999

We designed and fabricated p-type MOSFETs with floating gate in n-type well lesion and examined their photo characteristics. The fabricated MOBFETs showed a high photo-respsonse characteristics, indicating a possibility as a photo sensor. The structures of MOSFETs were changed as to the number of gate and channel. As the number of channel increased, the induced current by light source s increased. However, the effect of the number of gate was negligble on the photo-response characteristics of the device.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1966-1968
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• 1998

This paper describes a gate drive circuit for series connected IGBTs in high voltage applications. The proposed control criterion of the gate circuit is to actively limit the voltages during switching transients, while minimizing switching transient and losses. In order to achieve the control criterion, an analog closed loop control scheme is adopted. The performance of gate drive circuit is examined experimentally by the series connection of three IGBTs with conventional snubber circuits. The experimental results show the voltage balancing by an active control under wide variation in loads and imbalance conditions.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.35-39
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• 2009

A novel Helmholtz coil inductively coupled plasma(H-ICP) etcher is proposed and characterized for deep nano-scale CMOS technology. Various hardware tests are performed while varying key parameters such as distance between the top and bottom coils, the distance between the chamber ceiling and the wafer, and the chamber height in order to determine the optimal design of the chamber and optimal process conditions. The uniformity was significantly improved by applying the optimum conditions. The plasma density obtained with the H-ICP source was about $5{\times}10^{11}/cm^3$, and the electron temperature was about 2-3 eV. The etching selectivity for the poly-silicon gate versus the ultra-thin gate oxide was 482:1 at 10 sccm of $HeO_2$. The proposed H-ICP was successfully applied to form multiple 60-nm poly-silicon gate layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.04a
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• pp.39-40
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• 2008

We have examined post-annealing and passivation for the transparent bottom gate IGZO TFT having an inverse co-planar structure. The oxygen-vacuum two step annealing enhanced the field effect mobility up to 18 $cm^2$/Vsandthesub-threshold swing down to 0.2V/dec. However, the hysterysis and the bias stability problems could not be solved just by post-annealing. Thus, we have passivated the bottom gate IGZO TFTs with organic and inorganic materials. $Ga_2O_3$, $Al_2O_3$, $SiO_2$ and some polymer materials were effective materials for passivations. The hysterysis and the stability of the TFTs were remarkably improved by the passivations. We have manufactured the AMOLED panel with the transparent bottom gate IGZO TFT array successfully.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• Journal of Hydrogen and New Energy
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• v.15 no.4
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• pp.317-323
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• 2004

We fabricated a MISFET using Pd/NiCr gate for the detecting of hydrogen gas in the air and investigated its electrical characteristics. To improve stability and high concenntration sensitivity and remove the blister generated by the penetration of hydrogen atoms Pd/NiCr catalyst gate metal are used as dual gate. To reduce the gate drift voltage caused by the inflow of hydrogen, the gate insulators of sensing and reference FFET were constructed with double insulation layers of silicon dioxide and silicon nitride. The hydrogen response of MISFET were amplified with the difference of gate voltages of both MISFET. To minimize the drift and the noise, we used a OP177 operational amplifier. The sensitivity of the Pd/NiCr gate MISFET was lower than that of Pd/Pt gate MISFET, but it showed good stability and ability to detect high concentration hydrogen up to 1000ppm.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.461-463
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• 2009

We report on the fabrication of ZnO-based thin-film transistor (TFT) inverters with top and bottom gate structures with $Al_2O_3$ dielectrics grown by atomic layer deposition (ALD). Since the top gate ZnO-based TFT showed somewhat lower field effect mobility than that of the bottom gate device, our ZnO-based TFT inverters were designed with identical dimensions for both channels. This TFT inverter device demonstrated an high voltage gain at a low supply voltage of 5 V and clear dynamic behavior.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.17-19
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• 2004

The electrical properties of gate oxides grown in two different processes, which are in 10% nitrous oxide($N_2O$) and in dry oxygen, have been experimentally investigated and compared. It has been observed that the $SiC-SiO_2$ interface-trap density(Dit) measured in nitrided gate oxide has been tremendously reduced, compared to the density obtained from gate oxide grown in dry oxygen. The beneficial effects of nitridation on gate oxides also have been demonstrated in the values of total near interface-trap density and of forward-bias breakdown field. The reasons of these improvements have been explained.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.1-7
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• 2023

Large-size, organic light-emitting device (OLED) panels based on highly reliable gate driver circuits integrated using InGaZnO thin film transistors (TFTs) were developed to achieve ultra-high resolution TVs. These large-size OLED panels were driven by using a novel gate driver circuit not only for displaying images but also for sensing TFT characteristics for external compensation. Regardless of the negative threshold voltage of the TFTs, the proposed gate driver circuit in OLED panels functioned precisely, resulting from a decrease in the leakage current. The falling time of the circuit is approximately 0.9 ㎲, which is fast enough to drive 8K resolution OLED displays at 120 Hz. 120 Hz is most commonly used as the operating voltage because images consisting of 120 frames per second can be quickly shown on the display panel without any image sticking. The reliability tests showed that the lifetime of the proposed integrated gate driver is at least 100,000 h.