• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.921-926
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• 2003

This paper describes a new type of the spatial filter detector (SFD) with variable and multi-valued weighting function. This SFD called variable spatial filter detector with multi-valued weighting function (VSFDwMWF) uses current-mode circuits for noise resistance and high-resolution weighting values. Total weighting values consist of 7bit, 6-signal bit and 1-sign bit. We fabricate VSFDwMWF chip using Rohm 0.35${\mu}$m CMOS process. VSFDwMWF chip includes two-dimensional 10${\times}$13 photodiode array and current-mode weighting control circuit. Simulation shows the weighting values are varied and multi-valued by external switching operation. The layout of VSFDwMWF chip is shown.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.7 no.2
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• pp.91-99
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• 1998

This paper presents a methodology for identifying the cutter runout geometry in end milling process. Cutter runout is common but undesirable phenomenon in multi-tooth machining because it introduces variable chip loading to insert which results in a accelerated tool wear. amplification of force variation and hence enlargement vibration amplitude From understanding of chip load change kinematics, the analytical cutting force convolution model was formulated as the angular domain convolution model was formulated as the angular domain convolution of three dynamic cutting force component functions. By virtue of the convolution integration property, the frequency domain expression of the local cutting forces and the chip width density of the cutter. Experimental study is presented to validate the analytical model. This study provides the in-process monitoring and compensation of dynamic cutter runout to improve machining tolerance and surface quality for industrial application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.404-409
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• 2004

We fabricated photo-sensor for fluorescence detection in LOC. LOC is high throughput screening system. Our LOC screens biochemical reaction of protein using the immunoassay, and converts biochemical reaction into electrical signal using LIF(Laser Induced Fluorescence) detection method. Protein is labeled with rhodamine intercalating dye and finger PIN photodiode is used as photo-sensor We measured fluorescence emission of rhodamine dye and analyzed tendency of fluorescence detection, according to photo-sensor size, light intensity, and rhodamine concentration. Detection current was almost linearly proportional to two parameters, intensity and concentration, and was inversely proportional to photo-sensor size. Integrated LOC consists of optical-filter deposited photo-sensor and PDMS microchannel detected 50 (pg/${mu}ell$) rhodamine. For integrated LOC including light source, we used green LED as the light source and measured emitted fluorescence.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.09a
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• pp.55-85
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• 2000

MEMS(Micro Electro Mechanical System) technology. MEMS Inertial Sensors promise a new wide market for many areas -Challenge. significant cost reduction by wafer level packaging and testing. decreasing of power consumption by miniaturization. enhancing of performance and reliability. on-chip integration for multiplicity. MEMS is newly emerging technology.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.12-24
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• 2001

The key advantage of LTCC(low temperature co-fired ceramics) technology is the ability to integrate passive components such as resistors, capacitors, and inductors. More compact circuits with an increased scale of integration are needed with the development for advanced telecommunication system such as IMT-2000. LTCC technology can be obtained by removing these elements from the substrate surface to inside of ceramic body. And it can miniaturize the wireless phone through integration of planar patch antenna, duplexer, band pass filter, bias line, circuit of impedance matching and RF choke etc. Futhermore, with the multilayer chip process and its outstanding electrical material characteristics, LTCC is predestined for highly-integrated, cost effective wide band applications. This paper focuses on the general description of LTCC MCM technologies and the fabrication of the multilayer VCO module.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.3
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.