• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.86-93
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• 2008

A low-power, low-noise, highly-linear hybrid balun circuit is proposed for 2.4-GHz fully differential CMOS direct conversion receivers. The hybrid balun is composed of a passive transformer and loss-compensating auxiliary amplifiers. Design issues regarding the optimal signal splitting and coupling between the transformer and compensating amplifiers are discussed. Implemented in $0.18{\mu}m$ CMOS process, the 2.4 GHz hybrid balun achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart and +23 dBm of IIP3 only at a current consumption of 0.67 mA from 1.2 V supply. It is also examined that the hybrid balun can remarkably lower the total noise figure of a 2.4 GHz fully differential RF receiver only at a cost of 0.82 mW additional power dissipation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.29-36
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• 2009

In this paper, the design and implementation of LNA and down-mixer using 90 nm CMOS process are presented for 60 GHz band WPAN receiver. In order to extract characteristics of the transistor used to design each elements under the optimum bias conditions, the S-parameter of the manufactured cascode topology was measured and the effect of the RF pad was removed. Measured results of 3-stages cascode type LNA the gain of 25 dB and noise figure of 7 dB. Balanced type down-mixer with a balun at LO input port shows the conversion gain of 12.5 dB within IF frequency($8.5{\sim}11.5\;GHz$) and input PldB of -7 dBm. The size and power consumption of LNA and down-mixer are $0.8{\times}0.6\;mm^2$, 43 mW and $0.85{\times}0.85\;mm^2$, 1.2 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.41-46
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• 2007

A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.91-99
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• 2018

This paper has proposed a low-noise and high-linear RF receiver supporting TV white space from 470 MHz to 698 MHz), which is implemented in $0.13-{\mu}m$ CMOS technology. It consists of a low-noise amplifier, a RF band-pass filter, a RF amplifier, a passive down-conversion mixer, and a channel-selection low-pass filter. A low-noise amplifier and RF amplifier provide a high voltage gain to improve the sensitivity level. To suppress strong and nearby interferers, two RF filtering schemes have been performed by using a RF BPF and a down-conversion mixer. The proposed LPF has been based on the common-gate topology and adopted a bi-quad cell to achieve -24dB/oct characteristics. In addition, the RF receiver can support the overall TV band by controlling a LO frequency. The simulated results show a voltage gain of 56 dB, a noise figure of less than 2 dB, and an out-of-channel IIP3 of -2.3 dBm. It consumes 37 mA from a 1.5 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.408-415
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• 2007

A switched-gain controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8\;GHz$ UWB system. In high gain mode, measurement shows a power gain of 12.5 dB, an input IP3 of 0 dBm, while consuming only 8.13 mA of current. In low gain mode, measurement shows a power gain of -8.7 dB, an input IP3 of 9.1 dBm, while consuming only 0 mA of current.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.597-604
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• 2006

An ultrawideband(UWB) $3.1{\sim}5.15$ GHz low-noise amplifier employing a novel input matching circuit and feedback topology are presented. The proposed UWB amplifier is Implemented in $0.18{\mu}m$ RF CMOS technology. Measurements show a NF of $3.4{\sim}3.9$ dB, a power gain of $12.8{\sim}14$ dB, better than -9.4 of input matching and, an input IP3 of -1 dBm, while comsuming only 14.5 mW of power.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.900-905
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• 2009

A common drain feedback CMOS wideband LNA with current bleeding and input inductive series-peaking techniques is presented in this paper. DC coupling is adopted between cascode and feedback amplifiers, so that the gain and NF of the LNA can be dynamically controlled by adjusting the bleeding current. The fabricated LNA shows the bandwidth of 2.5 GHz. The high gain mode shows 17.5 dB gain with $1.7{\sim}2.8\;dB$ NF and consumes 27 mW power and the low gain mode has 14 dB gain with $2.7{\sim}4.0\;dB$ NF and dissipates 1.8 mW from 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.9
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• pp.915-921
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• 2013

This work presents a 77 GHz low noise amplifier(LNA) for automotive radar systems using 65 nm RF CMOS process. The LNA is composed of three stage common source amplifiers and includes transmission line matching networks. To reduce the time for three dimensional EM simulation, we optimize the transmission line impedance matching network using a pre-built EM library. The proposed compact simulation technique is confirmed by measurement results. The peak gain of the LNA is 10 dB at 77 GHz and input/output return losses are below -10 dB around the design frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.77-84
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• 2007

In this parer, a wideband low-noise amplifier (LNA) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion RF receivers. By exploiting the inverter-type transimpedance input stage with a 3rd-order Chebyshev matching network, the wideband LNA demonstrates the measured results of the -3dB bandwidth of 5.35GHz, the power gain (S21) of $12\sim18dB$, the noise figure (NF) of $6.9\sim10.8dB$, and the broadband input/output impedance matching of less than -10dB/-24dB within the bandwidth, respectively. The chip dissipates 32.4mW from a single 1.8V supply, and occupies the area of $0.56\times1.0mm^2$.