• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.28-36
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• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.494-503
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• 2003

In this paper, we propose the implementation techniques of IC card chipset that is compatible with international standard ISO-7816 and supports WindowsCE operating system to expropriate various electronic cash and credit card. This IC card interface chip set is composed with 32 bit ARM720T Core and AES(Advanced Encryption System) cryptography module for electronic commerce. Six IC card interfaces support T=0, T=1 protocol and two of them are used to interface with user card directly, the others are used for interface with SAM card. In addition, It supports a LCD controller and USB interface for host. We improved the performance about 70% than software based It card chip set and verified using Hynix 0.35um process.

• The Magazine of the IEIE
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• v.23 no.11
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• pp.89-100
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• 1996

A new stage-sliced pipiline structure is presented to design a high speed real time Global Positional Systems(GPS) applications. The CORDIC algorothm was revised to generate a pipeline structure, which will be used to produce a large amount of trigonometric computations rapidly. A stage-sliced approach was introduced to adjust the number of interative processes, and thereby to control the precision of computation results. Both the computation and the control circuits of the proposed architecture are included in a pipeline stage, which are intergrated into a stage slice. The circuit was prototyped using six FPGA chips : one is used for glue logics and five of the chips are used for pipeline slice implementation. A single FPGA chip comprising 7 pipeline stages provides one pipeline slice. To compensate and inter-slice time delay, dummy cycles are introduced in inter-slice signal exchanges.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.63-71
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• 2000

Infrared (IR) detector chip, which detects the IR radiation from all of the objects and converts to image signal, is usually fabricated using hybrid bonding technology with detector away and readout integrated circuit (ROIC). In this study, we designed the readout circuit and simulated its operations. Fabricating readout circuit chips, we measured operation results satisfying its design requirements in 6V supply voltage. After we mount the IR detector chip in the manufactured thermal image system, thermal images were implemented. The obtained thermal images for high and room temperature target objects are sufficiently recognizable. Using the low noise thermal Image system, we expect to obtain thermal images with higher temperature resolution.

• Journal of IKEEE
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• v.21 no.3
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• pp.272-275
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• 2017

Recently, semiconductor integration density enormously increases and its interconnection width is significantly narrowed, which leads to EMI (electromagnetic interference) problems on chip level. Chip manufacturer exploits TEM cell (transverse electromagnetic cell) to measure EMI on chip level, which requires PCB (printed circuit board) for measurement purpose. However, it is often neglected to consider that PCB patterns and other factors can affect on EMI measurement. In this paper, several test patterns are designed for different PCB design variables, and effects of PCB patterns on EMI measurement in TEM cell are analyzed. Based on these analyses, PCB design guidelines are also proposed to minimize the effects on EMI measurements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2020-2025
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• 2006

H.264/AVC is newest video coding standard of the ITU-T Video coding Experts Group and the ISO/IEC Moving Picture Expets Group. Recently H.264/AVC has been adopted as a video compression standard in DMB and multimedia equipments. In this paper, we propose a H.264/AVC intra frame decoder which can minimize the memory usage and chip size. The proposed intra frame decoder is described in VHDL language and simulated in model_sim. It was verified in chip level by downloading to XCV1000E FPGA chip.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.2
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• pp.79-84
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• 2007

This papar reports design and fabrication of CMOS temperature control circuit using MOSIS 0.25um-3.3V CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. Furthermore, the temperature coefficient of output voltage can be controlled by adjusting external bias voltage. This circuit my be applicable to the design of one-chip IC where quartz crystal resonator is mounted on CMOS oscillator chips.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.206-210
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• 2003

In this paper, we design standard cell libraries using the 0.18um deep submircom CMOS process, and port them into a P&R (Placement and Routing) CAD tool. A simple test chip has been designed in order to verify the functionalities of the 0.18um standard cell libraries whose technical process was provided by Anam semiconductor. Through these experiments, we have found that the new 0.18um CMOS process can be successfully applied to automatic digital system design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.362-368
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• 2001

본 논문에서는 두 개의 17비트 오퍼랜드를 radix-4 Booths 알고리즘을 이용하여 곱셈 연산을 수행하는 곱셈기를 설계하고 효율적인 풀커스팀 디자인에 대한 테스트 방법을 제안하였다. 클럭 속도를 빠르게 하기 위하여 2단파이프라인 구조로 설계하고 규칙적인 레이아웃을 위해 4:2 CSA(Carry Save Adder)를 사용하였다. 회로는 LG 반도체의 0.6-um 3-Metal N-well CMOS 공정을 사용하여 칩으로 제작되었다. 새로운 개념의 모듈레벨 고착 고장 모델을 제안하였고 제안한 테스트 방법을 사용하여 관찰해야 하는 노드의 수를 약 88% 줄여 효율적인 고장 시뮬레이션을 수행하였다. 설계된 곱셈기는 9115개의 트랜지스터로 구성되며 코어 부분의 레이아웃 면적은 약 1135*1545 um2 이다. 제작된 칩은 전원접압 5V에서 약 24MHz의 클럭 주파수로 동작한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.687-694
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• 1999

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.