• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.2
• /
• pp.123-128
• /
• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.12
• /
• pp.2933-2938
• /
• 2014

In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{\mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${\pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${\pm}5%$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.14 no.1
• /
• pp.37-42
• /
• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.15 no.2
• /
• pp.89-94
• /
• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.14 no.6
• /
• pp.479-486
• /
• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.73-81
• /
• 2012

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2176-2182
• /
• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

• Journal of IKEEE
• /
• v.16 no.4
• /
• pp.322-327
• /
• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.5
• /
• pp.531-537
• /
• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.6
• /
• pp.651-657
• /
• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.