• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.100-106
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• 1999

A new IBC(Island Body Contact) structure is introduced to SOI CMOS VLSI for stabilizing the body potential of the MOSFET without the additional area consumption. The improvement of the body contact effect is achieved by reducing the body resistance and the area is saved as the bodies of the MOSFETs are connected together. Its property as VLSI device is confirmed through the device simulations and the measurement.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.41-47
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• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• Journal of IKEEE
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• v.17 no.2
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• pp.214-220
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• 2013

Small area LDO (Low drop-out) regulator with pass transistor using body-driven technique is presented in this paper. The body-driven technique can decrease threshold voltage (Vth) and increase the current ID flowing from drain to source in current. The technique is applied to the pass transistor to reduce size of area and maintain the same performance as conventional LDO regulator. A pass transistor using the technique can reduce its size by 5.5 %. The proposed LDO regulator works under the input voltage of 2.7 V ~ 4.5 V and provides up to 150mA load current for an output voltage range of 1.2 V ~ 3.3 V.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1205-1206
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• 2008

본 실험에서는 CMOS 공정에서 사용하는 실리콘 트렌치 공정을 이용하여 분절된 트렌치 바디 접촉구조를 형성, 60 V급 전력 MOSFET 소자를 제작하였으며, 결과 소자의 면적을 증가시키지 않고도 제어되지 않은 유도성 스위칭 (UIS) 상황에서 낮은 전도 손실과 높은 항복 에너지 ($E_{AS}$)를 구현하였다. 분절된 트렌치 접촉구조는 소자의 사태 파괴시 n+ 소스 아래의 정공전류를 억제한다. 이는 트렌치 밑 부분에서부터 이온화 충돌이 일어나기 때문이며, 이는 기생 NPN 바이폴라 트랜지스터의 활성화를 억제하여 항복 에너지를 증가시킨다. 기존 소자의 항복 전압은 69.4 V이고 제안된 소자의 항복 전압은 60.4 V로 13% 감소하였지만, 항복 에너지의 경우, 기존소자가 1.84 mJ인데 반하여 제안된 소자는 4.5 mJ로 144 % 증가하였다. 트렌치의 분절 구조는 n+ 소스의 접촉영역을 증가시켜 온 저항을 감소시키며 트렌치 바디 접촉구조와 활성영역의 균일성을 증가시킨다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.28-36
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• 1998

We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1792-1797
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• 2007

This paper try to find root-cause of failure in a connector used in transmitting signals for throttle body control in automotives by analyzing possible failure causes and performing experiments to simulate the cable failure in field. The connector comprises fins, wires, and case moldings. The failure is due to degradation of initial clamping force required fixing fins and wires in the connector. Expansion and compression of the case molding material surrounding fins would cause the degradation. Investigations of strict initial claming force and control of thermal expansion property of the molding are required to prevent the failure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.87-93
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• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.6
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• pp.25-30
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• 2013

In nanoscale MOSFET technology, aging effects such as Negative Bias Temperature Instability(NBTI), Hot carrier Injection(HCI), Time Dependent Dielectric Breakdown (TDDB) and so on which affect circuit reliability can lead to severe degradation of digital circuit performance. Therefore, this paper has proposed the adaptive compensation circuit to overcome the aging effects of digital circuits. The proposed circuit deploys a power gating structure with variable power switch width and variable forward body-biasing voltage in order to adaptively compensate for aging induced performance degradation, and has been designed in 45nm technology.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.137-138
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• 2016

본 논문에서는 넓은 영전압 스위칭 범위와 작은 DC 오프셋 전류를 가지는 비대칭 하프-브릿지 컨버터를 제안한다. 기존의 비대칭 하프-브릿지 컨버터는 설계 시 홀드업 시간 만족을 위하여 정상 상태에서 극심한 비대칭 동작을 하게 된다. 이는 변압기의 큰 DC 오프셋 전류, 비대칭 전류 스트레스 등의 문제를 야기하며 이로 인하여 전반적인 변환 효율이 감소하게 된다. 이러한 문제점들을 해결하기 위하여, 제안하는 컨버터는 정상 상태에서 비대칭 동작을 최소화하고 낮은 입력전압에서 추가 스위치를 동작시킴으로써 커뮤테이션 구간을 줄여 전압이득을 높인다. 또한 추가 인덕턴스를 사용하여 영전압 스위칭 에너지를 키우고 추가 스위치의 내부 바디 다이오드를 이용하여 2차측 정류단의 전압 스트레스를 줄인다. 이를 통하여 높은 효율을 가지면서 작은 DC 오프셋 전류를 가지는 비대칭 하프-브릿지 컨버터를 제안하였으며, 500W의 프로토타입 컨버터를 제작하고 실험을 통해 이를 검증하였다.