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Design of a new adaptive circuit to compensate for aging effects of nanometer digital circuits

나노미터 디지털회로의 노화효과를 보상하기위한 새로운 적응형 회로 설계

  • 김경기 (대구대학교 전자전기공학부)
  • Received : 2013.10.02
  • Accepted : 2013.11.29
  • Published : 2013.12.31

Abstract

In nanoscale MOSFET technology, aging effects such as Negative Bias Temperature Instability(NBTI), Hot carrier Injection(HCI), Time Dependent Dielectric Breakdown (TDDB) and so on which affect circuit reliability can lead to severe degradation of digital circuit performance. Therefore, this paper has proposed the adaptive compensation circuit to overcome the aging effects of digital circuits. The proposed circuit deploys a power gating structure with variable power switch width and variable forward body-biasing voltage in order to adaptively compensate for aging induced performance degradation, and has been designed in 45nm technology.

나노크기 MOSFET 공정에서 회로의 신뢰도에 영향을 미치는 음 바이어스 온도 불안정성(NBTI), 핫 캐리어 주입(HCI), 시간 의존 유전체 파손(TDDB) 등과 같은 노화 현상들에 의해서 회로 성능의 심각한 저하를 가져올 수 있다. 그러므로, 본 논문에서는 디지털회로에서 발생할 수 있는 노화를 극복할 수 있는 적응형 보상 회로를 제안하고자 한다. 제안된 보상회로는 노화에 의해 감소하는 회로 성능을 적응적으로 보상해 주기 위해서 노화 정도에 따라 파워스위치 폭을 조절할 수 있고, 순방향 바디 바이어싱 전압을 걸어줄 수 있는 파워 게이팅 구조를 사용하여서 45nm의 공정기술에서 설계되었다.

Keywords

References

  1. J. Keane , D. Persaud and C. H. Kim "An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB", Proc. IEEE VLSI Circuits Conf., pp.108 -109 2009.
  2. Yeon-Bo Kim, Kyung Ki Kim, "The Impact of TDDB Failure on Nanoscale CMOS Digital Circuits", Journal of the Korea Industrial Information System Society, V. 17, No. 3, pp.27-34, July 2012. https://doi.org/10.9723/jksiis.2012.17.3.027
  3. Kyung Ki Kim, "Analysis of Electromigration in Nanoscale CMOS Circuits," Journal of the Korea Industrial Information System Society, V. 18, No. 1, pp.19-24, Feb. 2013. https://doi.org/10.9723/jksiis.2013.18.1.019
  4. Kyung Ki Kim, "Minimal Leakage Pattern Generator," Journal of the Korea Industrial Information System Society, V. 16, No. 5, pp.1-8, Dec. 2011.
  5. Kyung Ki Kim, "On-chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits" Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.57, no.1, pp.798-902, Oct.2010.
  6. Kyung Ki Kim, " Adaptive HCI-aware power gating structure" Quality Electronic Design (ISQED), 2010 11th International Symposium on, pp. 219-224, March.2010.
  7. Kyung Ki Kim, "Ultra-Voltage Power Gating Structure Using Low Threshold Voltage" Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol.56, no.1, pp.926-930, Dec.2009.
  8. S. Kim, S. Kosonocky, D. Knebel, "Understanding and minimizing ground bounce during mode transition of power gating structures", IEEE ISLPED, pp. 22-25, Aug. 2003.
  9. P. Royannez, et. al., "90nm low leakage SoC design techniques for wireless applications", IEEE International Solid-State Circuits Conference, pp. 138-139, Feb. 2005.

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