• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.499-508
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• 2016

Injection molding is a method for manufacturing many products, wherein a plasticized resin is injected into a mold at high pressure and hardened. According to the method, the product can be manufactured into various forms, and the mass production of up to tens of thousands of products is possible. The purpose of this study was to determine the process conditions for manufacturing a door latch for automobiles, through an analysis of the injection molding method. To calculate an appropriate injection flow for injection molding, a primary analysis for comparing the injection time, pressure, flow pattern, consolidation range, shear stress, shear rate, and weld line, as well as a secondary analysis for determining the conditions for stabilizing the molding temperature, holding pressure, and cooling process, were conducted. The characteristics of injection molding, and their influence on the product quality are discussed. No weld line and pores were observed on the products that had been manufactured based on the process conditions determined above. In addition, there were no flaws regarding the deformation compared to the prototype. Therefore, the manufacture of a product under the conditions determined in this study can reduce the defect rate compared to the existing production, and the process is also more competitive due to reduced production time.

• Journal of Applied Reliability
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• v.14 no.3
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• pp.147-151
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• 2014

An actuator latch device of a hard disk drive is installed for locking an actuator to hold a magnetic head parked in a parking zone. Applying an external force to the drive, the head can move away from the parking zone and destroy data on the disk. A magnet latching mechanism is used to prevent the actuator from moving when the computer is not in use. A permanent magnet holds the actuator when the head is in the parking zone. When the computer is turned on, the actuator has to overcome the latch magnet in order to move. A stronger latch magnet will hold the actuator adequately, but the actuator will not be released when unlocking is required. A breakthrough solution is needed to improve the reliability of the drive without any deterioration of its performance. In order to obtain the idea for resolving this technical contradiction, we analyse patents for actuator latch device of a hard disk drive. A practical way for solving contradictions in product development using TRIZ is proposed in this paper.

• Journal of IKEEE
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• v.13 no.1
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• pp.87-93
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• 2009

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.

• 전자공학회논문지 IE
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• v.44 no.2
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• pp.14-20
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• 2007

This paper presents quaternary D flip-flop with advanced performance. Quaternary D flip-flop is composed of the components such as thermometer code output circuit, EX-OR gate, bias inverter, transmission gate and binary D flip-flop circuit. The designed circuit is simulated by HSPICE in $0.35{\mu}m$ one-poly six-metal CMOS process parameters with a single +3.3V supply voltage. In the simulations, sampling frequencies is measured around 100MHz. The PDP parameters and FOM we estimated to be 59.3fJ, 33.7 respectively.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1155-1157
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• 2011

본 논문에서는 가전기기의 대기전력 저감을 위해 Capacitive Divider Power Supply(CDPS)로 전원을 공급받는 고효율 전원제어회로를 제안하였다. 이 제어회로는 220 V의 AC 전압을 높은 효율로 기기의 구동용 저전압 DC로 변환하기 위하여 기존의 변압기나 SMPS를 사용하는 대신 커패시터 분압기(Capacitive Divider)를 사용하여 전원을 공급하도록 제작되었으며, 대기 상태에서 교류전력선과 가전기기를 완전히 분리시킨 상태에서 적외선 수신기, MCU, 래치 타입 릴레이 등의 소자를 이용하여 기존 상용 리모컨으로도 전원제어가 가능하도록 설계되었다. 설계된 회로의 소비전력은 2.2 mW이며 본 논문에서 제안한 전원제어회로를 대기전력이 700 mW인 모니터에 적용하여 측정한 결과 대기전력이 7 mW로 낮아지는 것을 확인하였으며, 태양전지를 보조전원으로 추가 할 경우 태양전지에서 공급해주는 전력만큼 대기전력이 감소함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1046-1055
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• 1994

In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.865-868
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• 2001

We designed and fabricated a planner-type thermoelastic microactuator with a latch-up operation for optical switching. Latch-up actuation is prerequisite to implement an optical switch with low power consumption and high reliability. The proposed microactuator consists of four cantilever-shaped thermal actuators, four displacement linkages, two shallow arch-shaped leaf springs, a mobile shuttle mass with a micromirror, and four elastic boundaries. The structural layer of the planar microactuator is phosphorous-doped 12$\mu\textrm{m}$-thick polysilicon, and the sacrificial layer is LTO(Low Temperature Oxide) of 3$\mu\textrm{m}$thickness. The displacement of actuator is as large as 3$\mu\textrm{m}$when the length of actuation bar is 100$\mu\textrm{m}$in length at 5V input voltage. The proposed microactuators have advantages of easy assembly with other optical component by way of fiber alignment in the substrate plane, and its fabrication process features simplicity while retaining batch-fabrication economy.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.1-9
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• 2009

In this paper proposed a new method which adaptively eliminates comparator offsets using the threshold voltage shift by the Fowler-Nordheim stress. The method evaluates the sign of comparator offset and gives the FN stress to the stronger MOSFETs of the comparator, leading to offset reduction. We have used an appropriate stressing operation, named 'stress-packet', in order to converge the offset value to zero. We applied the method to the latch-type comparator which is prevalently used for DRAM bitline sense amplifier, and verified through experiments that offsets of the latch-type comparators are nearly eliminated with the stress-packet operations. We also discuss about the reliability issues that must be guaranteed for field application of this method.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.52-58
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• 2001

This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.