• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.7
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• pp.594-599
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• 2005

In this paper, we report the properties of Mo metal employed as PMOS gate electrode. Mo on $SiO_2$ was observed to be stable up to $900^{\circ}C$ by analyzing the Interface with XRD. C-V measurement was performed on the fabricated MOS capacitor with Mo Bate on $SiO_2$. The stability of EOT and work-function was verified by comparing the C-V curves measured before and after annealing at 600, 700, 800, and $900^{\circ}C$. C-V hysteresis curve was performed to identify the effect of fired charge. Gate-injection and substrate-injection of carrier were performed to study the characteristics of $Mo-SiO_2$ and $SiO_2-Si$ interface. Sheet resistance of Mo metal gate obtained from 4-point probe was less than $10\;\Omega\Box$ that was much lower than that of polysilicon.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.29-32
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• 2001

In this paper, the thermal oxidation behaviors and the electrical characteristics of the thermal oxide grown on SiC are discussed. For these studies the oxide layers with various thickness were on SiC in wet $O_2$ or dry $O_2$ at l15$0^{\circ}C$ and the MOS capacitors using the 350$\AA$ gate oxide grown in wet $O_2$ were fabricated and electrically characterized. It was found from the experimental results that the oxidation rate of SiC with the Si-face and with the carbon-face were about 10% and 50% of oxidation rate of Si. The C-V measurement results of the SiC oxide showed abnormal hysterisis properties which had ever been not observed for the Si oxide. And the hysterisis behavior was seen more significant when initial bias voltage was more negative or more positive. The hysterisis property of the SiC oxide was believed to be due the substantial amount of the deep level traps to exist at the interface between the oxide and the SiC substrate. The leakage of the SiC oxide was found to be one order larger than the Si oxide, but the breakdown strength was almost equal to that of the Si oxide.

• Electrical & Electronic Materials
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• v.4 no.1
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• pp.38-44
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• 1991

본 연구는 전기로에 의한 열 산화법에 의해 SiO$_{2}$(88[.angs.])와 ONO(89[.angs.])를 성장시켜 MIS capacitor를 제작한 후, 초 박막 유전체/실리콘 계면에서 전자파 간섭 효과를 실험적으로 비교 검토한 것이다. EWIE현상의 결과로서 첫째. 저 전계영역에 비해 고 전계영역에서 우세하며 둘째. SiO$_{2}$에 비해 ONO가 약하게 나타난다. 그러므로 ONO가 SiO$_{2}$보다 열 전송자 효과에 대한 저항성이 우수함을 알 수 있고 ULSI급의 게이트 절연막으로서의 실용가능성을 확인하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1401-1405
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• 2010

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $HfO_2$/p-Si structures. The $HfO_2$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. TEMAHf and $H_2O$ were used as the hafnium and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TEMAHf pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $HfO_2$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2420-2424
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• 2009

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $Al_2O_3/p-Si$ structures. The $Al_2O_3$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. Trimethylaluminum [$Al(CH_3)_3$, TMA] and $H_2O$ were used as the aluminum and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TMA pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $Al_2O_3$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• Journal of Electrochemical Science and Technology
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• v.8 no.2
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• pp.101-106
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• 2017

$Li_2SiO_3$ was used as a coating material to improve the electrochemical performance of $Li[Ni_{0.8}Co_{0.15}Al_{0.05}]O_2$. $Li_2SiO_3$ is not only a stable oxide but also an ionic conductor and can, therefore, facilitate the movement of lithium ions at the cathode/electrolyte interface. The surface of the $Li_2SiO_3$-coated $Li[Ni_{0.8}Co_{0.15}Al_{0.05}]O_2$ was covered with island-type $Li_2SiO_3$ particles, and the coating process did not affect the structural integrity of the $Li[Ni_{0.8}Co_{0.15}Al_{0.05}]O_2$ powder. The $Li_2SiO_3$ coating improved the discharge capacity and rate capability; moreover, the $Li_2SiO_3$-coated electrodes showed reduced impedance values. The surface of the lithium-ion battery cathode is typically attacked by the HF-containing electrolyte, which forms an undesired surface layer that hinders the movement of lithium ions and electrons. However, the $Li_2SiO_3$ coating layer can prevent the undesired side reactions between the cathode surface and the electrolyte, thus enhancing the rate capability and discharge capacity. The thermal stability of $Li[Ni_{0.8}Co_{0.15}Al_{0.05}]O_2$ was also improved by the $Li_2SiO_3$ coating.

• Journal of the Korean Ceramic Society
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• v.54 no.4
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• pp.340-348
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• 2017

$SiC_f/SiC$ composites were joined using a $60{\mu}m-thick$ $Ti_3AlC_2$ or $Ti_3SiC_2$ MAX phase tape. The filler tape was inserted between the $SiC_f/SiC$ composites containing a 12 wt.% $Al_2O_3-Y_2O_3$ sintering additive. The joining was performed to a butt-joint configuration at $1600^{\circ}C$ or $1750^{\circ}C$ in an Ar atmosphere by applying 3.5 MPa using a hot press. Microstructural and phase analyses at the joining interface confirmed the decomposition of $Ti_3AlC_2$ and $Ti_3SiC_2$, indicating the joining by solid-state diffusion. The results showed sound joining interface without the presence of cracks. Joining strengths higher than 150 MPa could be obtained for the joints using $Ti_3AlC_2$ or $Ti_3SiC_2$ at $1750^{\circ}C$, while those for joined at $1600^{\circ}C$ decreased to 100 MPa approximately without the deformation of the joining bodies. The thickness of initial filler tape was reduced significantly after joining because of the decomposition and migration of MAX phase owing to the plasticity at high temperatures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.197-198
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• 2009

This paper describes the Raman scattering characteristics of polycrystalline (poly) 3C-SiC films, which were deposited on the thermally oxidized Si(100) substrate by the atmosphere pressure chemical vapor deposition (APCVD) method according to growth temperature. TO and LO phonon modes to 2.0m thick poly 3C-SiC deposited at $1180^{\circ}C$ were measured at 794.4 and $965.7\;cm^{-1}$ respectively. From the intensity ratio of $I_{(LO)}/I_{(TO)}$ 1.0 and the broad full width half maximum (FWHM) of TO modes, itcan be elucidated that the crystallinity of 3C-SiC forms polycrystal instead of disordered crystal and the crystal defect is small. At the interface between 3C-SiC and $SiO_2$, $1122.6\;cm^{-1}$ related to C-O bonding was measured. Here poly 3C-SiC admixes with nanoparticle graphite with the Raman shifts of D and G bands of C-C bonding 1355.8 and $1596.8\;cm^{-1}$. Using TO mode of 2.0 m thick poly 3C-SiC, the biaxial stress was calculated as 428 MPa.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.05a
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• pp.39-43
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• 1993

Electricial characteristics of gate dielectrics prepared by reoxidation of thermal $SiO_2$ in nitrous oxide gas have been investigated. 10 and 19nm-thick oxides were reoxidized at temperatures of $900-1000^{\circ}C$ for 10-60 min in $N_2O$ ambient. As reoxidation proceeds, it is shown that nitrogen concentration at $Si/SiO_2$ interface increases gradually through the AES analysis. Nitrogen pile-up at $Si/SiO_2$ interface acts as a oxidant diffusion barrier that reduces the oxidation rate significantly. And it not only strengthen oxynitride structure at the interface but improve the gate dielectric qualities. Reliabilities of oxynitride films are conformed by the breakdown distributions and constant current stress technique. Therefore, the oxynitride films made by this process show a good promise for future ULSI applications.