A consideration for image improvement under the Born approximation in the microwave diffraction tomography is suggested by using a projection function. The limiting factors in the degrading reconstructed image due to Born approximation are identified in terms of projection function and its modification is suggested to improve the degraded image based upon the Born approximation. In order to verify the proposed method, the reconstructed images are shown by computer simulation from the back-scattered data of angular and frequency diversity for squared dielectric cylinder with a various relative dielectric constant. From simulation results, it was shown that the proposed method can lead to a fairly good improved image for a severe degraded one irrespective of homogeneous and inhomogeneous dielectric object. In the future, the analysis on the limitation of this method should be considered and performed by means of more quantitative method.

In this paper a push-push oscillator using DR (dielectric resonator) at K-band is designed and constructed. Two identical oscillators are arranged in a push-push configuration that has the frequency of oscillator that is twice frequency each oscillator. A dielectric resonator is placed at the input of an active two-port device(FET) yielding a stable frequency source. The oscillators realized with this technique exhibit excellent spectral purity and cancellation of fundamental frequency.

Recently, SSPAs(Solid-State Power Amplifiers) with high linearity and efficiency replace TWTAs (Traveling-Wave-Tube Amplifiers) in satellite transponders. In this paper, a power amplifier with maximum output power is designed and constructed using GaAs FET(MGF-1302) as a test model for the development of SSPAs. For conjugate matching of input and output network, transimission lines and stubs are optimized using microwave CAD program, LINMIC+. Power amplifier is realized on the teflon substrate($\in$S1rT=2.45) with a bandwidth of 1GHz at a center frequency of 8GHz. Maximum stable gain of simulation and simulation and experimental result is obtained 9.23, 7.65 dB, respectively.

The impedance matching properties of infinite planar arrays of rectangular waveguides with dielectric plug loading and sheath covering are studied here. The effects of several involved parameters on the impedance matching of the phased array antenna are investigated by calculating the reflection coefficients numerically. The improvement of impedance matching and the appearance of forced surface wave resonances are also discussed.

The design method of signal delay line system using indirect frequency synthesizer is presented. The variable signal delay line system with 2[nsec] step of delay time at center frequency 60[MHz], bandwidth 500[KHz] and range 5.24-5.81[x10S0-6Tsec] is designed and fabricated. The results were met with good characteristics to be variable delay time of average 2.01[nsec] per step.

Mutually pumped phase conjugator(MPPC) is experimentally investigated and analyzed in terms of fanning gratings of a photorefractive BaTiO$_3$ crystal. As considering the intensity-dependent absorption and coupling cofficients in photorefractive two wave mixing, the dependence of phase conjugate reflectivites on the incident angle, beam ratio, and total intensity in MPPC is analyzed.

In this paper, a new extended JPDA (Joint Probabilistic Data Association) tracking algorithm which has more excellent performance than that of the conventional JPDA algorithm in case of the tracking of crossing targets is proposed. In the proposed extended JPDA algorithm, the velocity parameters as well as the position parameters are included to compute the association probabilities between tracks and measurement data. Then the tracking performance of crossing targets is improved and the track bias of parallel moving targets can be reduced. Accordingly, in this paper, the new extended JPDA algorithm for multitarget tracking is proposed and its good performance is shown through the computer simulation. And, tracking performance of extended JPDA algorithm is also compared with that of JPDA algorithm with our noise model.

Polycrystalline silicon ingots were manufactured using the casting method for polycrystalline silicon solar cells. These ingots were cut into wafers and ten n$^{+}$p type solar cells were made through the following simple process` surface etching, n$^{+}$p junction formation, metalization and annealing. For the grain boundary passivation, the samples were oxidized in O$_2$ for 5 min. at 80$0^{\circ}C$ prior to diffusion in Ar for 100 min. at 95$0^{\circ}C$. The conversion efficiency of polycrystalline silicon solar cells made from these wafers showed about 70-80% of those of the single crystalline silicon solar cell and superior conversion efficiency, compared to those of commercial polycrystalline wafers of Wacker Chemie. The maximum conversion efficiency of our wafers was indicated about 8%(without AR coating) in spite of such a simple fabrication method.

Shallow $p^{+}-n,n^{+}-p$ diodes have been fabricated using rapid thermal diffusion by solid diffusion source and rapid thermal alloying with pure Aluminum. Diode area and junction depth are designed about 2.83$[\times}10^{-3}cm^{2}$ and 250nm, respectively. Electrical characteristics of $p^{+}-n$ diode show that the ideality factor is 1.04 and reverse current density is 29.3nA/$cm^{2}$, respectively. On the other hand, those of $n^{+}-p$ diode show that the ideality factor is 1.05 and reverse current density is 85.2pA/$cm^{2}$. The reverse currents are measured at 5V reverse bias after rapid thermal alloying for all the measurement.

Concurrent Junction process (simultaneous formation of a silicide and a junction on the implanted substrate) by Rapid Thermal Annealig has been investigated. Electrical and material properties of CoSi$_2$ films were analyzed with Alpha Step, 4-point probe, X-ray diffraction(XRD) and Scanning Electron Microscope(SEM). And CoSi$_2$ junctions were examined with Spreading Resistance probe in order to see the redistribution of electrically activated dopants and determined the junction depth. Two step annealing process, which was 80$0^{\circ}C$ for 30sec and 100$0^{\circ}C$ for 30sec in NS12T ambient was employed to form CoSi$_2$ and shallow junctions. Resistivity of CoSi$_2$ was turned out to be 11-15${\mu}$cm and shallow junctions less than 0.1$\mu$m were successfully formed by the process. It was found that the dopant concentration at CoSi$_2$/Si interface increased as decreasing the thickness of Co films in case of $p^{+}/n$ and $n^{+}/p$ junctions while the junction depth decreased as increasing CoSiS12T thickness in case of $p^{+}/n$ junction.

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.

In this pape, we designed and implemented a hardware accelerator for the generation of bit map font from Hangul outline font description for LBP (Laser Beam Printer) and screen applications Whole system was implemented as a double size PC/AT application board which consists of processing bolck and display block. The processing block has a master processor (MC68000)and two slave processors which are MC56001 and KAFOG chip responsible for the short vector generation. In the display block, TMS34061 was used for monitor display and GP425 was used for LBP print out. The resolution of the monitor is 640$\times$480 and that of LBP is 2385$\times$3390. The current system called KHGB90-B generates about 100 characters per second where each character consists of 32$\times$32 bits