In this paper, the properties of autocorrelation function of binary sequences are investigated. From these properties, the binary sequences which can be used for measurement of impulse response on fading channel are found by computer search. A receiver which can measure impulse response by use of these binary sequences is devised. This devised measurement system produces zero values of autocorrelation function for the all delays except zero sight.

Recently, in a variety of the application fields, it is interested in GPS receiver as the use of GPS(Global Positioning System) is increased. In this paer, we propose that a type of new receiver of a simple structure as GPS data receiver. This proposed receiver consists of RF stage, local C/A(Coarse/Acquisition) code generator, C/A code correlator, data demodulator and microprocessor controller as a GPS single channel data receiver using the L1 carrier . It is confirmed that the proposed receiver operates well as GPS raw data receiver through experiment.

The majority of problems to which FDTD is being applied involve open structure which require the appropriate scheme to terminate the computational domain. In particular, for the propagation problem of the outgoing waves, a certain type of boundary condition needs to be applied on outer boundaries of the computational domain to generate no reflected waves. In this paper, a new simple technique is presented, which allows the reduced computation time and excellent absorbing characteristics for normal and oblique incident waves on outer boundaries. To illustrate the validity of this method, a numerical calculation for monopole antenna is carried out and the results are compared to measured data. The time-domain properties for circular patch antennas are investicated.

A new vertical power MOSFET with over-current protection capability is proposed. The MOSFET consists of main power MOSFET cell, sensing MOSFET cell and lateral npn bipolar transistor. The proposed MOSFET may be fabricated by a conventional DMOS process without any additional fabrication step. Overcurrent state is sensed by the newly designed lateral bipolar transistor. Mixed-mode simulations proved that the overcurrent protection is achieved by the proposed MOSFET successfully with a small protection area less than 0.2 % of the total die area.

In this paper the driving-condition-dependent optical transmission characteristics of an STN LCD are studied. The optical transmission properties are measured for the applied voltage waveform is varied. Also, the optimum ranges of the M signal frequency and the frame frequency are investigated. An LCD is modeled by the equivalent circuit to study the effect of the parameter variation on the frequency response.

A laser diode(LD) structure consisting of a single 150$\AA$ $Al_{0.07}$Ga$_{0.93}$As quantum well active region operating at ${\lambda}$=809nm, cladded with an AlGaAs graded-index separate confinement heterostructure, has bes been grown by MOCVD. Temperature coefficient of wavelength is approximately 0.2nm $^{\circ}C$ for the diode. The active aperture consists of five emitters separated from each other by means of SiO$_{2}$ deposition and stripe formation, which creates insulating regions that channel the current to 100-$\mu$m-wide stripes placed on 450-$\mu$m centers. From a typical uncoated LD, the output power of 0.8W has been obtained at a 1$\mu$s, 1kHz pulsed current level of 2.0$\AA$, which results in about 64% external quantum efficiency. The threshold current density is 736A/cm$^{2}$ for the case of 500$\mu$m cavity length LD's. The measure of an internal quantum efficiency was 75.8% and the internal loss 4.83$cm^{-1}$ . Finally, 3.1W output power has been obtained at a 1$\mu$s, 1kHz pulsed current level of 9A from the 500$\mu$m-aperture LD array with 460-$\mu$m- cavity length.

In this paper, a new real-time optical image switching system based on the phase-typed BPEJTC is suggested. The phase filter mask which has the arbitrary position mapping function between input and output planes is constructed by using the modified JTPS of the BPEJTC. Then, the input image is convolved with this phase filter mask in the spatial frequency domain and through further Fourier transform the input image is switched to the new positions in the output correlation plane where the correlation peaks are occurred. And, based on the computer simulation results, the practical optical switched to the new positions in the output correlation plane where the correlation peaks are occurred. And, based on the computer simulation results, the practical optical switching system is opto-digitally constructed and through some experiments on image switching the possiblity of real-time implementation of the multiple optical image switching system by using the BPEJTC is suggeste.

In this paper, atmospheric turbulence and absorption under clear weather condition, which affect the optical satellite up-link communication between geo-satellites and earth station, were studied. In case of the up-link communication, the received optical power is weakened by pointing loss caused by beam tilt which is the main effect of turbulent atmosphere. This pointing loss directly has relation to the diameter of optical transmitting antenna. From the inverse proportion of the pointing and spaced loss, it is the regions where the diameter of transmitting antenna increases abruptly and the efficient design of transmitting antenna is impossible. In case of using channel coding, it was shown that the peak value of diameter moved to the lower regions of elevation angle with increasing the coding gain and its width was also decreased. In case of considering both coding gain and transmission rate on the design of transmitting antenna, it was known that more coding gain was necessary as transmission rate was increased.

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

In this paper, we present a high-level synthesis system that generates area-efficient RT-level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps , and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. Experimental results show the effectiveness of the proposed algorithm. When compared with previous approaches for several benchmarks available from literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.

The evaluation of the logic capability and the library generation method of the multiplexor-based logic module is described. Optimizing logic module for silicon area and logic capability is essential to build a efficient FPGAs(Field-Programmable Gate Arrays). Because the multiplexor-based logic module can implement a large number of functions, it presents difficulties for library-based approaches. However, the logic functions of the logic module can be significantly reduced by lmiting the number of variables and sum-of-products and by removing same functions with different variable ordering using algorithm presented in this paper.

This paper describes a development of the PLD design tool in considering with a device fitting. To design digital circuit with PLDs, several steps in the developed PLD design tool are needed such as Boolean description step, pin map step, FUSE map and JEDEC steps ... etc. Especially, we have considered the device fitting to design large digital circuits with PLDs developed the device fitting algorithms based on the PLD device fitting and compared with the results of a another PLD design tool(PALASM). Also, we have proved that the developed PLD design tool is successfully implemented by the connection with a PLD writer(ALL-07), in the case of design digital circuits.