In this paper, we hve compare the performance of DAR(Dynamic Adaptive Routing) with that of FSR(Flooding Search Routing) to select an adequate routing protocol in circuit-switched networs. As a performance factor, we have considered call setup time, which is the key factor of performance evaluation in circuit switched networks. We have evaluated the performance of two methods in grid topology circuit-switched networks using a commn channel signaling scheme, as application examples. As results, FSR method shows better performance than DAR method under light traffic load, when the number of links by which call has passed increases, but DAR method represents better performance than FSR method under heavy traffic load or large networks because of redundant packets.

In this paper, the linearized power amplifier using digital adaptive predistorter is implemented in order to restrict spectral spreading and adjacent channel interference. The linearized systems is composed of a DSP56001 processor that executes predistortion in baseband. 90.deg. phase shifter, power splitter/combiner, quadrature modulator/demodulator of 360MHz band, and nonlinear amplifier. A ${\pi}$/4-shift QPSK is used to modulate digital random signals. As the quantized power of baseband signal and the output of amplifier are fed to the predistorter, and predistorting values are calculated using an adaptive algorithm. In the experiment, a peak to sidelobe ratio of the linearized amplifier is improved up to 15dB in comparison with conventional nonlinear amplifier, which means that the distortion of transmitted signal is decreased and adjacent channel interference was reduced.

In this paper, transmitter and receiver modules for free space optical interconnection are implemented and characterized. In the transmitter module, bias circuitry which inject current into the direct modulated laser diode is fabricated and in the receiver module, p-i-n diode is integrated with an MMIC amplifying stage. Laser diode has a direct-modulated bandwidth of 2 GHz at 1.4 Ith bias while p-i-n diode and amplifying stage has a bandwidth of 1.3 GHz and 1.5 GHz, repectively. Optical interconnection has a bandwidth of 1.3 GHz and linearly transmit modulated voltage signal up to 1.5 Vp-p. Measured loss of optical interconnection is 5dB which is composed of optoelectronic conversion loss of 15 dB, electrical impedance mismatch loss of 6.7 dB in transmitter module and gain of 18 dB in receiver module. Seperation between transmitter and receiver can be extended up to 50 cm by using a lens.

In this paper, we present an antenna which can be used for subsurface continuous wave electromagnetic probing. Its input impedance and transmission coefficient of the two port scattering parameters, S$_{21}$, are calculated numerically and the numerical results are compared with measured values from laboratory scale-down experiment. Scale-down experiemtn results using this antenna show that we can detect a metallic pipe, which has 0.8 cm in diameter and buried at a depth of 5.7cm in saline solution, in frequency range from 200 MHz to 1000 MHz.

Aluminum films were deposited by the pyrolysis of triisobutylaluminum(TIBA) in a cold wall LPCVD system for the metallization of high level IC. the selectivity on Si/SiO2 substrate and the contact resistance on submicron contacts were investigated. The carbon free aluminum film could be obtained when the aluminum film was deposited at low substrate temperature. Contact resistances of CVD Al/n+ Si contacts whose contact size was 0.5 .mu.m werre as low as 20~40.OMEGA./ea, which is 30~50% of contact resistance obtained by sputtering technique.

GaAs and AlGaAs layers were grown by Molecular Beam Epitaxy (MBE) to fabricate hith performance GaAs MESFETs. Optimum growth temperatures were found to be 600$^{\circ}C$ from their Hall measurement data. MESFETs with the gate legth of 1${\mu}$m and the gate width of 100.mu.m were fabricated on the MBE-grown GaAs layters which has i-GaAs buffer layer and characterized. Knee volgate and mazimum transconductance of the devices were 1V, 224mS/mm, respectively. Cut-off frequency at on-wafer measuring pattern was measured to be 18 GHz. The MESFET with the 1${\mu}$m -thick i-Al$_{0.3}Ga_{0.7}$As buffer layer between nactive and i-GaAs was fabricated on order to reduce the leakage current which flows through the i-GaAs buffer layer. Its output resistance was 2.26 k${\Omega}$.mm which increased by a factor of 15 compared with the MESFET without i-Al$_{0.3}Ga_{0.7}$As buffer layer.

This study is to apply the theory of fatigue fracture to solder joints under thermal cyclic loading and predict life of solder joint to failure. A 62Sn-36Pb-2Ag solder was used in this study. Tensile tests were preformed at temperatures of 15.dec. C, 50.dec. C and 85.dec. C in order to find terms of crack length "a". plastic strain range ""${\Delta}{\varepsilon}_p$" and temperature "T". Solder joint under thermal cyclic loading was analyzed by FEM. this FEM analysis together with the crack growth rate will provide the capability of the fatigue life prediction of solder joints and enhance the reliability od solder joint.

The effects of sulfur treatments on the barrier heithts of Schottky contacts and the interface-state density of metal-insulator-semiconductor (MIS) capacitors on InP have been investigated. Schottky contacts were formed by the evaporation of Al, Au, and Pt on n-InP substrate before and after (NH$_{4}$)$_{2}$S$_{x}$ treatments, respectively. The barrier height of InP Schottky contacts was measured by their current-voltage (I-V) and capacitance-voltage (C_V) characteristics. We observed that the barrier heights of Schottky contacks on bare InP were 0.35~0.45 eV nearly independent of the metal work function, which is known to be due to the surface Fermi level pinning. In the case of sulfur-treated Au/InP ar Pt/InP Schottky diodes, However, the barrier heights were not only increased above 0.7 eV but also highly dependent on the metal work function. We have also investigated effects of (NH$_{4}$)$_{2}$S$_{x}$ treatments on the distribution of interface states in Si$_{3}$N$_{4}$InP MIS diodes where Si$_{3}$N$_{4}$ was provided by plasma enhanced chemical vapor deposition (PECVD). The typical value of interface-state density extracted feom 1 MHz C-V curve of sulfur-treated SiN$_{x}$/InP MIS diodes was found to be the order of 5${\times}10^{10}cm^{2}eV^{1}$. This value is much lower than that of MiS diodes made on bare InP surface. It is certain, therefore, that the (NH$_{4}$)$_{2}$S$_{x}$ treatment is a very powerful tool to enhance the barrier heights of Au/n-InP and Pt/n-InP Schottky contacts and to reduce the density of interface states in SiN$_{x}$/InP MIS diode.

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

In this paper, $As_{40}Se_{50-x}S_[x}Ge_{10}$(x=0, 25, 35, at.%) bulk and thin films, to develope device of reversible hologram, proved amorphous by X-RD analysis. On the thin films with composition rate, as Se-doped-quantity increased, absorption edge shifted to long wavelength, and we found that reversible photodarkening effect occurred when thin films are exposed and annealed. Optical energy gap was larger when thin films are annealed than exposed. In this effect thin films structurally stabilized by annealing. It is to formed grating hologram by the bragg method on the $As_{40}Se_{15}S_[35}Ge_{10}$ thisn films with the best transmittance properties As polariging angle grew larger, we found that maximum diffraction efficiency became smaller, and obtained it of 4.5% on the thin fim thicknesss of 0.6 m, polarizing angle of 40$^[\circ}$ and exposing for 20sec.

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

We used CMOS current mirror and differenial amplifier to find out how the degradation of each devices in circuit affect total circuit performance. The devices in circuit wer degraded by hot-carrier generated during circuit operation and total circuit performance were changed according to the change of each device parameters. To examine the circuit performance phenomena of current mirror, we analyzed three diffent kinds of current mirrors and made correlation model between circuit performance and stressed device parameters, and compare hot-carrier immunity of these circuits. Also we analyzed how the performance of differential amplifier degraded from the initial value after hot-carrier stress incircuit operations.

SOI(Silicon-On-Insulator) pn 다이오드의 최적 수평길이($L_{dr}$)와 항복전압에 대한 해석적인 표현식을 n' 츠리프트 영역의 농도 및 두께, 매몰 산화막 두께의 함수로 유도하였다. 최적($L_{dr}$은 n'n접합의 수직 방향전계에 의한 항복전압과 n'np'접합으 수평방향 전계에 의한 항복전압이 같다는 조건으로부터 유도하였다. 해석적 표현식의 결과는 PISCESII를 사용한 시뮬레이션 결과와 잘 일치하였다.

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

Aluminum films were chemically vapor deposited for the metallization of the integrated circuits and the spiking characteristics of the direct CVD Al/Si contacts were investigated. When the aluminum was formed by CVD uniform consumption of the substrate silicon was observed, which is quite different from the phenomena observed in sprttered Al. Silicon consumption occured during the deposition of CVD Al and the erosion depth of the silicon was several hundred $\AA$ when the continuous films were formed on the substrate while much less erosion of the silicon occured when the Al were formed in islands. When the submicron contacts were selectively plugged, contact resistances were very low and the erosion depth of the silicon was trivial.

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.

A linear BiCMOS operational transconductance amplifier (OTA) is described. It consists of a CMOS linear transconductor and a bipolar translineear current gain cell followed by three CMOS current mirrors. The proposed circuit has comparable linearity and temperature stability but superior dc characteristics to its bipolar counterpart. A test circuit with a transconductance of 47.3$\mu$s has been simulated. Simulation results show that a linearity error of less than $\pm$1 percent over an input volgate range from -1.0 to 1.0 V and a output dc offset current as small as-3.6 nA can be obtained.

This paper proposes new algorithms to solve canonical piecewise-linear equations with linear partitions and illustrates their efficiency through the analysis of resistive network. The basic idea of the proposed algorithm is to find the best next guess, closest to the actual solution, at each Newton-Raphson (N-R) iteration by comparing the images of nest guess candidates and that of the actual solution. The proposed algorithm can reduce the number of the N-R iterations rquired for convergence greatly, compared to the actual solution, at each Newton-Raphson (N-R) iteration by comparing the images of next guess candidates and that of the actual solution. The proposed algorithm can reduce the number of the N-R iterations required for convergence greatly, compared to the Katzenelson algorithm. When applied to analyzing test circuits, the proposed algorithm required 8 to 20 times fewer N-R iterations and 5 to 10 times less CPU time than the Katzenelson algorithm, depending on the size of the circuits. The experimental results also exhibit that the efficiency of the proposed algorithm over the Katzenelson algorithm increases as the number of the piecewise-linear regions for the representation of the circuit.