In this paper, we evaluate the performance of DD-bardner (decision-directed gardner) algorithm. We derive an analytic gain of the thiming detector that is a function of SNR and an excess bandwidth, and verify the result by simulation. We also compare the DD-gardner algorithm with the bardner algorithm with respect to tracking performance and jitter performance under low SNR and a residual frequency component.

The trellis shaping is the method of selecting a minimum weight sequence from an equivalent class of possible transmitted sequences. It is perforemed by searching through the trellis diagram of a shaping convolutional code Cs. A shaping gain of the order of 1dB may be obtained with a simple 4-state shaping code. But when the rellis shaping is applied to multi-dimensional constellation, the shaping gain is decreased and the transmission delay is increased, which make it difficult to apply the trellis shaping to multi-dimensional constellation. In this paper, in order to solve these problems, the shell mapping algorithm is used for the mapper in the proposed trellis shaping. The simulatio result shows that the proposed trellis shaping is better than coventional trellis shaping to multi-dimensional constellation. In this paper, in order to solve these problems, the shell mapping on multi-dimensional costellation with respect to shaping gain and transmission delay. And the constellation expansion ratio (CER) and the capacity of transmitted injformation are identical to those of conventional trellis shaping on multi-dimensional constellation.

A digital logic demodulator for binary FSK signals is presented. The operation is based on the quadricorrelator which is known as an ideal frequency detector. The demodulator is especially suitable for high-speed application, and it can be easily implemented in integrated circuit. Computer simulation results show that the performance of the receiver with digital demodulator converges to that of analog quadricorrelator receiver as the number of mixing axes is increased and the optimum bandwidth depending on a modulation index is slightly wider than that of analog demodulator.

The methodology is suggested to measure the quality of service in telecommunications. Through questionnaire, the subjective evaluation of users is surveyed, and quantified by MOS method. The MOS mehtod has some problems in interpretation which are mentioned in this paper. The cumulative percent curve is proposed to evaluate the quality of service. As an example, the image quality of G3 facsimile is measured.

A method for computing effectiv ebandwidth of aggregated varable bit rate (VBR) moving picture experts group (MPEG) video traffic is proposed. To compute statistical characteristics of aggregated MPEG traffic, first we split input MPEG traffic into I, B, and P frame traffics and aggregate respective I, B, and P frame traffics according to the frame type. Second statisticsal characteristics of the aggregated MPEG traffic are obtained using those of aggregated I, B, and P frame traffics. The effective bandwidth of the aggregated I frame traffic is computed by using the gaussian bound. Using the modified equivalent capacity, we obtain the effective bandwidths of aggregated B and P frame traffics and then compute the effective bandwidth of the combined B and P frame traffic. Finally the effective bandwidth of the aggregated MPEG traffic is computed by adding the gaussian bound of the aggregated I frame traffic and modifed equivalent capacity of combined B and P frame traffic. Computer simulation shows that the proposed method estimates effective bandwidth of the aggregated MPEG traffic well.

This paper focuses on the necessities of interworking and dervation of the requirements of interworking system for interworking between 64 Kbps based N-ISDN (narrowband ISDN) and B-ISDN(broadband ISDN). Furthermore, the design and the implementation of IWF (interworking function) are presentd. We analyze two ISDN signalling systems, and propose the architecture of interworking system. And then we make the baisc call procedure model between N-ISDN and B-ISDN, and verify the dynamic behaviors through the reachability tree of petri net. IWF is designed and implemented for transforming the differences between the two signalling systems. The operational confirmity of th eimplemented program was confirmed by the local test method. The performance of IWF was evaluated throguh the simulation language SLAM-II. As the result of evaluation shows, we confirm that the processing delay is maintained within 3 ms under the utilization 0.9.

In this paper, we find the values of near-end crosstalk coefficient in striplines of a FR-4 multilayer PCB by an analytic method and a HSPICE simulation method, and define calcualtion errors in an analytic method and define the application range, and simualte near-end crosstalk coefficients of the FCT (fast CMOS TTL) in complicated striplines by HSPICE and analyze near-en crosstalk coefficients in relation to dielectric thickness and trace spaces of striplines. As a result, we analyze coupling structure of the near-end crosstalk in the coplicated sstriplines that are impedance matched and define a coupling formula of near-end crosstalk coefficients in general complicated striplines. Especially, it is approximated in the layout grade rule.

Sattering problem of electromagnetic waves by periodic strip grating with two dielectrics over a ground plane in case of oblique incidence and arbitrary polarization is analyzed by the vector floquet mode expansion method and the moment mehtod from the viewpoint of soft and hard boundary value problem. To confirm proposed analysis methods, we examine the solution convergence for the scattering problem. And some numerical results of artificially soft and hard surfaces using the structure filled with single dielectric slab between periodic strip grating and gorund plane is compared with previous results. Some interesting results for soft and hard surfaces using periodic strips loaded with two layered dielectric slabs over a ground plane are given.

In this paper, a very efficient CAD algorithm is proposedd where rhodes formulae combined with distributed lowpass prototype filter in order to design the corrugated waveguide harmonic rejection filters accurately. The proposed algorithm resolves effectively the problem of proximity effect without any optimiation or iterative design process by using the internally convexed corrugated structure. A 13-section tapered corrugated lowpass filter has been designed by the proposed algorithm and fabricated. The experimental results are in good agreement with the calculated results.

A numerical method for scattering of electromagnetic waves from a periodic strip grating over a grounded dielectric slab is considered for TE and TM polarization cases from the viewpoints of both reflection grating problem and leaky wave antenna problem. The analysis is based on a mode expansion method, floquet's theorem, and the method of moments. Numerical results involving some combinations of geometric parameters are presented in terms of complex propagation constant (kd-$\beta$d diagram), radiation pattern, and relative scattered powers of spectral modes. In particular, the relationship between complex propagatio constnat form the viewpoint of leaky wqve antenna problem and Off-bragg and bragg blazing phenomena from the viewpoint of reflecton graing problem is investigated.

A thin film of aluminum for ultra large scale integrated circuits metalization has been deposited on TiN and SiO$_{2}$ substrates by plasma assisted chemical vapor deposition using DMEAA (dimenthylethylamine alane) as a precursor. The effects of plasma on surface topology and growth characteristics were investigated. Thermal CVD Al could not be got continuous films on insulating subsrate such as SiO$_{2}$. However, it was found that Al films could be deposited on SiO$_{2}$ substate without any pretreatments by the hydrogen plasma for pyrolysis of DMEAA. Compared to the thermal CVD, PACVD films showed much better reflectance and resistance on TiN and SiO$_{2}$ substrate. We obtained mirror-like PACVD Al film of 90% reflectance and resistance on TiN and SiO$_{2}$ substrates. We obtained mirror-like PACVD Al film of 90% reflectance on TiN substrate. Excellent conformal step coverage was obtained on submicron contact holes ;by the PACVD blanket deposition.

Monte carlo method is especially a useful method for the analysis of thermal noise of semiconductor devices since the time dependence of microscopic details is simulated directly. Recently, a mthod for the calculation of the instantaneous currents of 2-dimensional devices, which is numerically more accurate than the conventional method, has been proposed using the generalized ramo-shockley theorem. Using this mehtod we investage the validity of the existing thermal noise theories of field-effect transistors. First, the 1-dimensional analysis of thermal noise theories of field-effect transistors. First, the 1-dimensional analysis of thermal noise theories of field-effect transistors. First, the 1-dimensional analysis of thermal noise using ramo-shockley theorem is shown to be applicable to 2 dimensional devices if the frequency of interest is low enough. The correlation between electrons in different regions of th echannel is shown not to be negligible. And we also obtian the spatial map of the noise in the channel region. By doing so, we show that the steady state nyquist theorem is the correct theory rather than the theory by van der ziel et.al.

A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8$\mu$m CMOS process. In this design, a FVC and a 2nd - order passive filter are added to the conventional charge-pump PLL to improve the acquisition time. The dual-rijng VCO(voltage controlled oscillator) realized in this paper has a frequency range form 208 to 320MHz. Integrated circuits have been fully tested and analyzed in detail and it is proved that pull-in speed is enhanced with the use fo FVC. In VCO range from 230MHz to 310MHz, experimental results show that realized PLL exhibits 4 times faster pull-in speed than that of conventional PLL.

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

We report on the static and dynamic characteristics of optically modulated resonant tunneling diode oscillator (RTDO) formed in double-barrier quantum-well structure. Under the illumination of Ti:Sapphire laser, the dc current-voltage (I-V) curves of RTDO shifted towared lower voltages. This characteristic was found to odify the series resistance, negtive differential resistance, capacitance, and the inductance of the RTDO. As a result, the resonant frequency of TRDO centered at 5.302 GHz was found to decrease about 20 MHz under the laser illumination. At a constnat bias voltage, the oscillation frequency decreased linearly as the laser power was increased.

In this paper, the theoretical analysis and the computer simulation of a new modified cochran's triangular interferometer as an incoherent holography, which can eliminate bias and conjugate image problems of the conventional cochran's triangular interferometer, are spresented. In other words, it is theoretically derived by using jones matrix operation that bias and conjugate image can be removed by adding simple optical components including a polarizing beam splitter, wave plates, and linear polarizers to the conventional with a point source, we demonstrated the validity of the suggested method by comparing the modified cocharan's triangular interferometer with the conventional one.

We have designed and implemented an optoelectronic hardware of binary phase extraction joint transform correlator (BPEJTC) which provides higher peak-to-sidelobe ratio than many other versions of JTC that has been published so far and does not produce correlation peaks due to intra-class association, to construct a multi-target tracking system. The digital processing unit controlling the entire system plays the part of modifying and binarizing the joint transform power spectrum (JTPS) and the optical processing unit is mainly used to take fourier transform operations. Some experimental results conducted by designed system along with its architecture showed the processing rate of 6 frames per second, thereby the potential applicability of the proposed system to real-time multitarget tracking system is given.

A new pathlength deviation detection technique which is composed of michelson interferometer is described and verified experimentally. The technique uses a sub-threshold biased visible laser diode of 20$\mu$m coherence length as a low-coherent light source. And for zeroth-order fringe(which is the largest among fringes) identification we used a piezoelectric transducer with a large modulation smplitude, which enables without the need of constant velocity scanning, to distinguish reflection surfaces separated by more than 10$\mu$m with a resolution of less than half-wavelength.

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

This paper describes several algorithms for technolgoy mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improved the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as merging fanin, unified reduction and multiple disjoint decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.