• 한국생산제조학회지
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• 제23권3호
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• pp.230-236
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• 2014

Wafer level package technology is added to the surface of wafer circuit packages to create a semiconductor technology that can minimize the size of the package. However, in conventional packaging, warpage and fracture are major concerns for semiconductor manufacturing. We optimized the wafer dam design using a finite element method according to the dam height and heat distribution thermal properties. The dam design influences the uniform deposition of the image sensor and prevents the filling material from overflowing. In this study, finite element analysis was employed to determine the key factors that may affect the reliability performance of the dam package. Three-dimensional finite element models were constructed using the simulation software ANSYS to perform the dam thermo-mechanical simulation and analysis.

• 마이크로전자및패키징학회지
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• 제21권1호
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• pp.31-39
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• 2014

최근 모바일 응용 제품에 사용되는 반도체 패키지는 고밀도, 초소형 및 다기능을 요구하고 있다. 기존의 웨이퍼 레벨 패키지(wafer level package, WLP)는 fan-in 형태로, I/O 단자가 많은 칩에 사용하기에는 한계가 있다. 따라서 팬 아웃 웨이퍼 레벨 패키지(fan-out wafer level package, FOWLP)가 새로운 기술로 부각되고 있다. FOWLP에서 가장 심각한 문제 중의 하나는 휨(warpage)의 발생으로, 이는 FOWLP의 두께가 기존 패키지에 비하여 얇고, 다이 레벨 패키지 보다 휨의 크기가 매우 크기 때문이다. 휨의 발생은 후속 공정의 수율 및 웨이퍼 핸들링에 영향을 미친다. 본 연구에서는 FOWLP의 휨의 특성과 휨에 영향을 미치는 주요 인자에 대해서 수치해석을 이용하여 분석하였다. 휨을 최소화하기 위하여 여러 종류의 epoxy mold compound (EMC) 및 캐리어 재질을 사용하였을 경우에 대해서 휨의 크기를 비교하였다. 또한 FOWLP의 주요 공정인 EMC 몰딩 후, 그리고 캐리어 분리(detachment) 공정 후의 휨의 크기를 각각 해석하였다. 해석 결과, EMC 몰딩 후에 발생한 휨에 가장 영향을 미치는 인자는 EMC의 CTE이며, EMC의 CTE를 낮추거나 Tg(유리천이온도)를 높임으로서 휨을 감소시킬 수 있다. 캐리어 재질로는 Alloy42 재질이 가장 낮은 휨을 보였으며, 따라서 가격, 산화 문제, 열전달 문제를 고려하여 볼 때 Alloy 42 혹은 SUS 재질이 캐리어로서 적합할 것으로 판단된다.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권6호
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• pp.271-277
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• 2002

In this paper, a MEMS silicon package is newly designed, fabricated for HMIC, and characterized for microwave and millimeter-wave device applications. The proposed package is fabricated by using two high resistivity silicon substrates and surface/bulk micromachining technology. It has a good performance characteristic such as -20㏈ of $S_11$/ and -0.3㏈ of $S_21$ up to 20㎓, which is useful in microwave region. It has also better heat transfer characteristics than the commonly used ceramic package. Since the proposed silicon MEMS package is easy to fabricate and wafer level chip scale packaging is also possible, the production cost can be much lower than the ceramic package. Since it will be a promising low-cost package for mobile/wireless applications.

• 센서학회지
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• 제16권5호
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• pp.325-330
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• 2007

For the application to optic devices, wafer level package including spacer with particular thickness according to optical design could be required. In these cases, the uniformity of spacer thickness is important for bonding strength and optical performance. Packaging process has to be performed at low temperature in order to prevent damage to devices fabricated before packaging. And if photosensitive material is used as spacer layer, size and shape of pattern and thickness of spacer can be easily controlled. This paper presents polymer bonding using thick, uniform and patterned spacing layer of SU-8 2100 photoresist for wafer level package. SU-8, negative photoresist, can be coated uniformly by spin coater and it is cured at $95^{\circ}C$ and bonded well near the temperature. It can be bonded to silicon well, patterned with high aspect ratio and easy to form thick layer due to its high viscosity. It is also mechanically strong, chemically resistive and thermally stable. But adhesion of SU-8 to glass is poor, and in the case of forming thick layer, SU-8 layer leans from the perpendicular due to imbalance to gravity. To solve leaning problem, the wafer rotating system was introduced. Imbalance to gravity of thick layer was cancelled out through rotating wafer during curing time. And depositing additional layer of gold onto glass could improve adhesion strength of SU-8 to glass. Conclusively, we established the coating condition for forming patterned SU-8 layer with $400{\mu}m$ of thickness and 3.25 % of uniformity through single coating. Also we improved tensile strength from hundreds kPa to maximum 9.43 MPa through depositing gold layer onto glass substrate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.379-380
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• 2008

This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.124-128
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• 2001

We apply for the first time a low cost and loss wafer level packaging technology for RF-MEMS device. The proposed structure was simulated by finite element method (FEM) tool (HFSS of Ansoft). S-parameter measured of the package shows the return loss (S11) of 20dB and the insertion loss (S21) of 0.05dB.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.357-358
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.209-210
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• 2008

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1702-1703
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• 2011

MEMS 소자의 Wafer level Package 관련하여 Deep cavity를 가진 Cap Wafer와 Polymer bonding 중 cavity 단차로 인한 Polymer Patterning 및 접합 불량의 어려움을 극복할 수 있는 새로운 공정 flow를 제안하였다. Cavity를 형성할 때 사용하는 Si deep etching Mask인 기존의 Photoresist를 접합용 감광성 Polymer로 대체하고, cavity 형성 후, 별도의 추가 공정 없이 이 Polymer를 이용해 Wafer bonding을 진행하였다. 이를 통해 cavity 단차에 따른 문제를 해결함과 동시에 공정이 단순하고 제작 비용이 저렴하며, 신뢰성 있는 Wafer level Package를 구현하였다.