Journal of the Korean Society of Manufacturing Technology Engineers (한국생산제조학회지)

The Korean Society of Manufacturing Technology Engineers (한국생산제조학회)
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Wafer Level Package Design Optimization Using FEM

공정시간 및 온도에 따른 웨이퍼레벨 패키지 접합 최적설계에 관한 연구

  • Ko, Hyun-Jun (Graduate School of NID Fusion Technology, Seoul National University of Science Technology) ;
  • Lim, Seung-Yong (Graduate School of NID Fusion Technology, Seoul National University of Science Technology) ;
  • Kim, Hee-Tea (School of Mechanical Design and Automation Engineering, Seoul National University of Science Technology) ;
  • Kim, Jong-Hyeong (School of Mechanical Design and Automation Engineering, Seoul National University of Science Technology) ;
  • Kim, Ok-Rae (Korea Institute of Industrial Technology)
  • Received : 2014.03.10
  • Accepted : 2014.05.27
  • Published : 2014.06.15
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Abstract

Wafer level package technology is added to the surface of wafer circuit packages to create a semiconductor technology that can minimize the size of the package. However, in conventional packaging, warpage and fracture are major concerns for semiconductor manufacturing. We optimized the wafer dam design using a finite element method according to the dam height and heat distribution thermal properties. The dam design influences the uniform deposition of the image sensor and prevents the filling material from overflowing. In this study, finite element analysis was employed to determine the key factors that may affect the reliability performance of the dam package. Three-dimensional finite element models were constructed using the simulation software ANSYS to perform the dam thermo-mechanical simulation and analysis.

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References

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