• Title/Summary/Keyword: total graph

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TOTAL DOMINATION NUMBER OF CENTRAL TREES

  • Chen, Xue-Gang;Sohn, Moo Young;Wang, Yu-Feng
    • Bulletin of the Korean Mathematical Society
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    • v.57 no.1
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    • pp.245-250
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    • 2020
  • Let γt(G) and τ(G) denote the total domination number and vertex cover number of graph G, respectively. In this paper, we study the total domination number of the central tree C(T) for a tree T. First, a relationship between the total domination number of C(T) and the vertex cover number of tree T is discussed. We characterize the central trees with equal total domination number and independence number. Applying the first result, we improve the upper bound on the total domination number of C(T) and solve one open problem posed by Kazemnejad et al..

A Study of Non-Intrusive Appliance Load Identification Algorithm using Complex Sensor Data Processing Algorithm (복합 센서 데이터 처리 알고리즘을 이용한 비접촉 가전 기기 식별 알고리즘 연구)

  • Chae, Sung-Yoon;Park, Jinhee
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.17 no.2
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    • pp.199-204
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    • 2017
  • In this study, we present a home appliance load identification algorithm. The algorithm utilizes complex sensory data in order to improve the existing NIALM using total power usage information. We define the influence graph between the appliance status and the measured sensor data. The device identification prediction result is calculated as the weighted sum of the predicted value of the sensor data processing algorithm and the predicted value based on the total power usage. We evaluate proposed algorithm to compare appliance identification accuracy with the existing NIALM algorithm.

A Study on the Efficient Task Scheduling by the Reconstructed Task Graph (태스크 그래프의 재구성에 의한 효율적 태스크 스케줄링에 관한 연구)

  • Byun, Seung-Hwan;Yoo, Kwan-Jong
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.9
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    • pp.2235-2246
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    • 1997
  • This paper presents an effective heuristic task scheduling algorithm for multiprocessor systems. To execute task scheduling effectively which is defined as an allocation of m's tasks onto n's processors(m > n), several problems almost at NP-hard should be cleaned up. The purpose of the task scheduling obtains the minimum execution time by mapping the tasks on a system topology or reduces the total execution time to give a minimum system topology. In order to solve this problem, in this paper, the task scheduling is done by redefining a task graph to a reconstructed task graph (RTG). An RTG is obtained by merging or copying nodes to equal the number of nodes on each level of the task graph to the number of processors of the system topology and then directly scheduled to the system topology. This method obtains a fast scheduling time and a simple scheduling method, and near-optimal execution time without executing steps such as the refinement step and the duplication step after the task scheduling.

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Forecasting Late Blight of Potatoes at the Alpine Area in Korea (한국의 고랭지대에 있어서의 감자역병 발생예찰에 관하여)

  • Hahm Y. I.;Hahm B. H.;Franckowiak J. D.
    • Korean journal of applied entomology
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    • v.17 no.2 s.35
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    • pp.81-87
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    • 1978
  • Late blight incited by Phytophthora infestans (Mont.) de Bary, is an important problem for seed potato prodcution in Korea. At the alpine Daekwanryeong area, unprotected potatoes are often defoliated within 14 days after late blight is first observed in the field. Since regular spraying can control late blight, the forecasting service is needed for timely initiation of the spraying program. Climatological data and notes on late blight incidence were recorded during 1970-1977 at the Alpine Experiment Station. The moving graph method using 7-day average mean temperature and 7-day total rainfall did not give highly accurate forecasts. Adding data on relative humidity and 7-day average minimum temperature increased the usefulness of the moving graph. Yields of late blight susceptible varietieties in sprayed plots were related to late blight occurrence and to the rainfall distribution pattern.

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A Relative Nodal Displacement Method for Element Nonlinear Analysis (상대 절점 변위를 이용한 비선형 유한 요소 해석법)

  • Kim Wan Goo;Bae Dae sung
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.29 no.4 s.235
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    • pp.534-539
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    • 2005
  • Nodal displacements are referred to the initial configuration in the total Lagrangian formulation and to the last converged configuration in the updated Lagrangian furmulation. This research proposes a relative nodal displacement method to represent the position and orientation for a node in truss structures. Since the proposed method measures the relative nodal displacements relative to its adjacent nodal reference frame, they are still small for a truss structure undergoing large deformations for the small size elements. As a consequence, element formulations developed under the small deformation assumption are still valid for structures undergoing large deformations, which significantly simplifies the equations of equilibrium. A structural system is represented by a graph to systematically develop the governing equations of equilibrium for general systems. A node and an element are represented by a node and an edge in graph representation, respectively. Closed loops are opened to form a spanning tree by cutting edges. Two computational sequences are defined in the graph representation. One is the forward path sequence that is used to recover the Cartesian nodal displacements from relative nodal displacement sand traverses a graph from the base node towards the terminal nodes. The other is the backward path sequence that is used to recover the nodal forces in the relative coordinate system from the known nodal forces in the absolute coordinate system and traverses from the terminal nodes towards the base node. One open loop and one closed loop structure undergoing large deformations are analyzed to demonstrate the efficiency and validity of the proposed method.

A Relative for Finite Element Nonlinear Structural Analysis (상대절점좌표를 이용한 비선형 유한요소해석법)

  • Kang, Ki-Rang;Cho, Heui-Je;Bae, Dae-Sung
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2005.11a
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    • pp.788-791
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    • 2005
  • Nodal displacements are referred to the Initial configuration in the total Lagrangian formulation and to the last converged configuration in the updated Lagrangian formulation. This research proposes a relative nodal displacement method to represent the position and orientation for a node in truss structures. Since the proposed method measures the relative nodal displacements relative to its adjacent nodal reference frame, they are still small for a truss structure undergoing large deformations for the small size elements. As a consequence, element formulations developed under the small deformation assumption are still valid fer structures undergoing large deformations, which significantly simplifies the equations of equilibrium. A structural system is represented by a graph to systematically develop the governing equations of equilibrium for general systems. A node and an element are represented by a node and an edge in graph representation, respectively. Closed loops are opened to form a spanning tree by cutting edges. Two computational sequences are defined in the graph representation. One is the forward path sequence that is used to recover the Cartesian nodal displacements from relative nodal displacements and traverses a graph from the base node towards the terminal nodes. The other is the backward path sequence that is used to recover the nodal forces in the relative coordinate system from the known nodal forces in the absolute coordinate system and traverses from the terminal nodes towards the base node. One closed loop structure undergoing large deformations is analyzed to demonstrate the efficiency and validity of the proposed method.

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Automatic Placement and Routing System for Gate Array (게이트 어레이의 자동 배치, 배선 시스템)

  • 이건배;정정화
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.5
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    • pp.572-579
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    • 1988
  • In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

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A Fuzzy Vehicle Scheduling Problem

  • Han, Sang-Su;Lee, Kyo-Won;Hiroaki Ishii
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1998.06a
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    • pp.666-668
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    • 1998
  • In this paper, we consider a bi-objective vehicle routing problem to minimize total distance traveled and maximize minimum integrated satisfaction level of selecting desirable routes in an fuzzy graph. The fuzzy graph reflects a real delivery situation in which there are a depot, some demand points, paths linking them, and distance and integrated satisfaction level are associated with each route. For solving the vi-objective problem we introduce a concept of routing vector and define non-dominated solution for comparing vectors. An efficient algorithm involving a selection method of non-dominated solutions based on DEA is proposed for the vehicle routing problem with rigid distance and integrated satisfaction level.

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Vertex Coloring based Slot Reuse Scheduling for Power Line Communications

  • Yoon, Sung-Guk
    • Journal of Electrical Engineering and Technology
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    • v.10 no.5
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    • pp.2135-2141
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    • 2015
  • Power line communication (PLC) is one of the major communication technologies in smart grid since it combines good communication capability with easy and simple deployment. As a power network can be modeled as a graph, we propose a vertex coloring based slot reuse scheduling in the time division multiple access (TDMA) period for PLCs. Our objective is to minimize the number of assigned time slots, while satisfying the quality of service (QoS) requirement of each station. Since the scheduling problem is NP-hard, we propose an efficient heuristic scheduling, which consists of repeated vertex coloring and slot reuse improvement algorithms. The simulation results confirm that the proposed algorithm significantly reduces the total number of time slots.

Optimized Adoption of NVM Storage by Considering Workload Characteristics

  • Kim, Jisun;Bahn, Hyokyung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.1
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    • pp.1-6
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    • 2017
  • This paper presents an optimized adoption of NVM for the storage system of heterogeneous applications. Our analysis shows that a bulk of I/O does not happen on a single storage partition, but it is varied significantly for different application categories. In particular, journaling I/O accounts for a dominant portion of total I/O in DB applications like OLTP, whereas swap I/O accounts for a large portion of I/O in graph visualization applications, and file I/O accounts for a large portion in web browsers and multimedia players. Based on these observations, we argue that maximizing the performance gain with NVM is not obtained by fixing it as a specific storage partition but varied widely for different applications. Specifically, for graph visualization, DB, and multimedia player applications, using NVM as a swap, a journal, and a file system partitions, respectively, performs well. Our optimized adoption of NVM improves the storage performance by 10-61%.