• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2008.11a
• /
• pp.21-22
• /
• 2008

$SF_6/O_2$ 플라즈마 에칭을 통한 반도체 칩의 3차원 집적에 응용되는 through-silicon-via (TSV) 구조형성 연구를 수행하였다. Si via 형상은 $SF_6$, $O_2$의 가스 비율과 에칭이 되는 Silicon 기판의 온도에 의존함을 알수 있었다. 또한 Si via 형상에서 최소의 언더컷 (undercut) 과 측벽에칭 (local bowing) 은 black Si이 나타나는 공정조건에서 나타남을 확인하였다. 더 나아가 저온을 이용한 via 형성시 via 측벽에 형성되는 passivation layer와 mask의 성질이 저온으로 인해 high-aspect-ratio를 갖는 via를 형성할 수 있음을 알 수 있었다.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.2
• /
• pp.65-74
• /
• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2016.11a
• /
• pp.128-128
• /
• 2016

Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

• Journal of Welding and Joining
• /
• v.24 no.2
• /
• pp.64-70
• /
• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.4
• /
• pp.19-23
• /
• 2012

Silicon substrate for light emitting diodes (LEDs) has been the tendency of LED packaging for improving power consumption and light output. In this study, a low cost and high throughput Si through via fabrication has been demonstrated using a wet etching process. Both a wet etching only process and a combination of wet etching and dry etching process were evaluated. The silicon substrate with Si through via fabricated by KOH wet etching showed a good electrical resistance (${\sim}5.5{\Omega}$) of Cu interconnection and a suitable thermal resistance (4 K/W) compared to AlN ceramic substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.1
• /
• pp.23-28
• /
• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2009.10a
• /
• pp.171-172
• /
• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• The Journal of Korean Academy of Prosthodontics
• /
• v.41 no.1
• /
• pp.20-34
• /
• 2003

Novel methods producing supplementary and prosthetic material by cutting or discharge processing via computer design have been proposed as alternatives for traditional casting methods and are being utilized for commercial purposes. The CAD/CAM system used in dentistry can be classified into three-dimensional input of target values, restoration design, and material processing. The marginal fidelity in production of In-Ceram core has important clinical implications and is a key consideration issue in CAD/CAM production as well. Through this research, the author arrived at the following conclusion aaer conducting comparison analysis of marginal fidelities between the In-Ceram core produced via CAD/CAM and that produced through the traditional method ; 1. In the cases of mesial, distal, and lingual margins, the core margins via CAD/CAM produced lower values than those via the traditional method, but the differences were found to be statistically insignificant. 2. In the case of labial flange, the core margins via CAD/CAM produced lower values than those via the traditional method and the differences were found to be statistically significant. (p<0.05) 3. In comparision with overall marginal fidelity, the core margins via CAD/CAM produced lower values than those via the traditional method, but the differences were found to be statistically insignificant. 4. Among the core margins produced via the traditional method did not have statistically significant differences but fir those produced via CAD/CAM had statistically significant differences between labial and lingual sides and between labial and mesial sides. (p <0.05).

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.6
• /
• pp.312-316
• /
• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.24 no.12
• /
• pp.57-63
• /
• 2010

The efficiency of LED package is increasing by applying the high power, and a existing lighting is changing as the LED lighting. However, many problems have appeared by heat. Therefore, in order to solve thermal problems, LED lighting is designing in several ways, but the advantages of LED lighting is fading due to increase the prices and volumes. In this study, we try to improve the thermal performance by formation of via holes. The junction temperature and thermal resistance in the FR4-PCB with via-holes of 0.6[mm] was excellent in experiment and FR4-PCB with Via-holes of 0.6[mm] was excellent in simulation without solder. Further, the thermal resistance and the optical properties can be improved through a formation of via-holes.