• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1706-1711
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• 1989

Unit processes for the fabrication of HEMT(high electron mobility transistor)was studied and the optimum conditions of them were applied to the fabrifcation of a discrete HEMT device. The HEMT with a nominal gate-source spacing of 3.6\ulcorner and a gate length of 2.8\ulcorner showed a transconductance of 46.1mS/mm and a threshold voltage of -0.29V. A source-drain voltage of 2.0V for a saturation current of 35mA/mm was achieved.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.73-76
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• 2020

The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantum-mechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.1-7
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• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• Journal of IKEEE
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• v.22 no.1
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• pp.98-103
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• 2018

The CNTFET, which is widely recognized as a next-generation semiconductor, has a structure that can improve performance by positioning CNTs between the source and drain of a conventional MOSFET. However, positioning CNTs increases the complexity of a CNTFET's structure, and the process variation changes the complex structure into various shapes; so, when CNTFET device performance is analyzed, it requires more computation than that of a conventional MOSFET. These problems greatly increase the simulation time necessary for the analysis, and sometimes that analysis cannot be performed using an existing tool; they are therefore important obstacles to designing a circuit using a CNTFET. In this study, we will show that the existing Linear Programming methodology can be utilized to solve the long simulation time problem and discuss the effect of the suggested method in detail. Simulation results show that the Linear Programming method can reduce the number of simulation about 2.5 times when the maximum number of CNT is changed from 6 to 12.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.167.2-167.2
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• 2015

고 이동도(~10 cm/Vs), 낮은 공정온도 및 높은 투과율 등의 특성을 갖는 산화물 반도체는 저 소비전력, 대면적화 및 고해상도 LCD Panel에 적합한 재료로서 현재 일부 Mobile Panel 및 TFT-LCD Panel의 양산에 적용되고 있으나, 향후 UHD급(4 K, 8 K)의 대형, 고해상도 Panel에의 적용을 위해서는 30 cm2/Vs 이상의 고 이동도 재료의 개발 및 저 저항 배선의 적용에 따른 소자 신뢰성의 개선이 필요하다. Cu는 대표적인 저 저항 배선 재료로 일부 양산에 적용되고 있으나, Cu 전극과 산화물 반도체의 계면에서 Cu원자의 확산 및 Cu-O 층의 형성에 의한 소자 특성 저하의 문제가 있다. 본 연구에서는 고 이동도의 In doped-ZTO계 산화물 반도체를 기반으로 채널 층과 Cu source-Drain layer의 계면에서의 Cu element의 거동 및 TFT 소자 특성과의 상관관계를 고찰하고, 계면에 형성된 Cu-O layer에 대해 높은 전자 친화도를 갖는 Ca element를 첨가에 의한 TFT 소자 특성의 변화를 관찰하였다. 본 연구에서는 이러한 효과로 인한 소자 신뢰성의 향상을 기대하였으며, 우선 In doped-ZTO 채널 층에 Cu와 CuCa 2at% source-drain을 적용한 TFT 특성을 확인하였다. 그 결과, Cu는 Field-effect mobility: ~17.67 cm2/Vs, Sub-threshold swing: 0.76 mV/decade 및 Vth:, 4.40 V의 결과가 얻어졌으며 CuCa 2at%의 경우 Field-effect mobility: ~17.84 cm2/Vs, Sub-threshold swing: 0.86 mV/decade 및 Vth:, 5.74 V의 결과가 얻어졌다. 소자신뢰성 측면에서도 Bias Stress의 변화량 ${\delta}Vth$의 경우 Cu : 4.48 V에 대해 CuCa 2at% : 2.81 V로 ${\delta}Vth$:1.67 V의 개선된 결과를 얻었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.4
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• pp.484-491
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• 2008

In this paper, we design and fabricate the L-band high speed pulsed HPA using LDMOS FET. And we propose the high voltage and high speed switching circuit for LDMOS FET. The pulsed HPA using LDMOS FET is simpler than using GaAs FET because it has a high gain, high output power and sin81e voltage supply. LDMOS FET is suitable for pulsed HPA using switching method because it has $2{\sim}3$ times higher maximum drain-source voltage(65 V) than operating drain-source voltage($V_{ds}=26{\sim}28\;V$). As results of test, the output peak power is 100 W at 1.2 GHz, the rise/fall time of output RF pulse are 28.1 ns/26.6 ns at 2 us pulse width with 40 kHz PRF, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Journal of the Korean Vacuum Society
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• v.6 no.4
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• pp.326-336
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• 1997

From the concept that the ion implantation-induced defect is one of the major factors in determining source/drain junction characteristics, high quality ultra-shallow $p^+$-n junctions were formed through the control of ion implantation-induced defects in silicon substrate. In conventional process of the junction formation. $p^+$ source/drain junctions have been formed by $^{49}BF_2^+$ ion implantation followed by the deposition of TEOS(Tetra-Ethyl-Ortho-Silicate) and BPSG(Boro-Phospho-Silicate-Glass) films and subsequent furnace annealing for BPSG reflow. Instead of the conventional process, we proposed a series of new processes for shallow junction formation, which includes the additional low temperature RTA prior to furnace annealing, $^{49}BF_2^+/^{11}B^+$ mixed ion implantation, and the screen oxide removal after ion implantation and subsequent deposition of MTO (Medium Temperature CVD oxide) as an interlayer dielectric. These processes were suggested to enhance the removal of ion implantation-induced defects, resulting in forming high quality shallow junctions.