ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지

A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications

  • Received : 2004.06.11
  • Published : 2004.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

Keywords

References

  1. IEEE Trans. Electron Devices v.42 Experimental $0.25-{\mu}m-Gate$ Fully Depleted CMOS/SIMOX Process Using a New Two-Step LOCOS Isolation Technique Ohno, T.;Kado, Y.;Harada, M.;Tsuchiya, T.T.
  2. Electron Device Lett. v.15 Modeling the I-V Characteristics of Fully Depleted Submicrometer SOI MOSFET’s Hsiao, T.C.;Kistler, N.A.;Woo, J.C.S.
  3. Int. Electron Device Meet. Technical Digest A 50 nm Depleted-Substrate CMOS Transistor (DST) Chau, R.;Kavalieros, J.;Doyle, B.;Murthy, A.;Paulsen, N.;Lionberger, D.;Barlage, D.;Arghavani, R.;Roberds, B.;Doczy, M.
  4. IEEE Trans. Electron Devices v.44 Characteristics of SOI FET's Under Pulsed Conditions Jenkins, K.A.;Sun, J.Y.C.;Gautier, J.
  5. Symp. VLSI Tech. Dig. Comprehensive Study on AC Characteristics in SOI MOSFETs for Analog Applications Tseng, Y.C.;Huang, W.M.;Monk, D.;Diaz, D.;Ford, J.M.;Woo, J.C.S.
  6. J. Korean Phys. Soc. v.40 Effects of Shallow Trench Isolation on Silicon-on-Insulator Devices for Mixed Signal Processing Lee, Hyeok-Jae;Park, Young-June;Min, Hong-Shick;Lee, Jong-Ho;Shin, Hyung-Soon;Sun, Woo-Kyung;Kang, Dae-Gwan
  7. VLSI Tech. Dig. Robust Process Integration of $0.78m^2$ Embedded SRAM with NiSi Gate and Low-K Cu Interconnect for 90 nm SoC Applications Kim, Y.W.;Ahn, J.H.;Park, T.S.;Oh, C.B.;Lee, K.T.;Kang, H.S.;Lee, D.H.;Ko, Y.G.;Cheong, K.S.;Jun, J.W.;Liu, S.H.;Kim, J.;Nam, J.L.;Ha, S.R.;Park, J.B.;Song, S.A.;Suh, K.P.
  8. Jpn. J. Appl. Phys. v.34 Thermal Agglomeration of Thin Single Crystal Si on $SiO_2$ in Vacuum Ono, Y.;Nagase, M.;Tabe, M.;Takahashi, Y.
  9. Solid State Devices and Materials Fully Depleted SOI CMOS Device with Raised Source/Drain for 90 nm Embedded SRAM Technology Oh, M.H.;Park, C.H.;Kang, H.S.;Oh, C.B.;Kim, Y.W.;Suh, K.P.
  10. J. Korean Phys. Soc. v.41 A Novel Structure MOSFET's Fabricated by Using SiGe Selective Epitaxial Growth Method and Laser Induced Atomic Layer Doping Method Lee, Yong-Jae;Choi, Young-Shig;Bea, Ji-Chel
  11. J. Korean Phys. Soc. v.40 Fabrication of a $0.2-{\mu}m$ Ultra-Thin SOI Inverted Sidewall Recessed Channel CMOS with Single-Type Polysilicon Gate Woo, Dong-Soo;Park, Boo-Sik;Lee, Jong-Duk;Park, Byung-Gook
  12. IEEE J. Solid-State Circuits v.22 Static-Noise Margin Analysis of MOS SRAM Cells Seevinck, E.;List, F.J.;Lohstroh, J.