• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.15-18
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• 2003

Ta-Ti metal alloy is proposed for alternate gate electrode of ULSI MOS device. Ta-Ti alloy was deposited directly on $SiO_2$ by a co-sputtering method and good interface property was obtained. The sputtering power of each metal target was 100W. Thermal and chemical stability of the electrode was studied by annealing at $500^{\circ}C$ and $600^{\circ}C$ in Ar ambient. X-ray diffraction was measured to study interface reaction and EDX(energy dispersive X-ray) measurement was performed to investigate composition of Ta and Ti element. Electrical properties were evaluated on MOS capacitor, which indicated that the work function of Ta-Ti metal alloy was ${\sim}4.1eV$ compatible with NMOS devices. The measured sheet resistance of alloy was lower than that of poly silicon.

• Journal of the Korean institute of surface engineering
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• v.38 no.1
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• pp.44-48
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• 2005

We prepared nickel silicide layers from p-Si(l00)/SiO₂(2000 Å)/poly-Si(700 Å)/Ni(400 Å) structures, feasible for gates in MOSFETs, by annealing them from 500℃～900℃ for 30 minutes. We measured the color coordination in visible range, cross sectional micro-structure, and surface topology with annealing temperature by an UV-VIS-IR spectrometer, field effect scanning electron microscope(FE-SEM), and scanning probe micro-scope respectively. We conclude that we may identify the nickel silicide by color difference of 0.90 and predict the silicide process reliability by color coordination measurement. The nickel silicide layers showed similar thickness while the columnar grains size and surface roughness increased as annealing temperature increased.

• Korean Journal of Materials Research
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• v.21 no.2
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.569-574
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• 2007

In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.39-42
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• 2000

As gate dimensions continue to shrink below $0.2{\mu}m$, improving CD (Critical Dimension) control has become a major challenge during CMOS process development. Anti-Reflective Coatings are widely used to overcome high substrate reflectivity at Deep UV wavelengths by canceling out these reflections. In this study, we have investigated Batchtype system for PECVO SiOxNy as Anti-Reflective Coatings. The Singletype system was baseline and Batchtype system was new process. The test structure of Singletype is SiON $250{\AA}$ + Cap Oxide $50{\AA}$ and Batchtype is SiON $250{\AA}$ + Cap Oxide $50{\AA}$ or N2O plasma treatment. Inorganic chemical vapor deposition SiOxNy layer has been qualified for bottom ARC on Poly+WSix layer, But, this test was practiced on the actual device structure of TiN/Al-Cu/TiN/Ti stacks. A former day, in Batchtype chamber thin oxide thickness control was difficult. In this test, Batchtype system is consist of six deposition station, and demanded 6th station plasma treatment kits for N2O treatment or Cap Oxide after SiON $250{\AA}$. Good reflectivity can be obtained by Cap Oxide rather than N2O plasma treatment and both system of PECVD SiOxNy ARC have good electrical properties.

• The Magazine of the IEIE
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• v.42 no.7
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• pp.26-38
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• 2015

고집적화를 위한 Floating Gate NAND 개발과정에서 몇 차례 기술적 한계상황에 직면하였었지만, Air-Gap, Double patterning, Multi-level Cell, Error Correction Code과 같은 breakthrough idea 을 활용하여 1Xnm까지 성공적인 scale-down 을 하였고 10nm 까지도 바라보고 있지만, 10nm 미만으로는 적절한 방안을 찾지 못한 상황입니다. CTD 의 3D NAND Flash는 Aspect Ratio, Poly channel의 intrinsic 특성, Data 보존 능력 등 해결 해야 할 issue 들이 남아 있지만, F.G Flash 의 지난 20년간 Lesson-learn 과 Band engineering, Channel Si, PUC 의 요소기술 개발 및 System algorithm 개발, QLC 개발 등을 통하여 F.G Flash를 넘어 지속적인 Cost-down 이 가능할 것입니다.

• ETRI Journal
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• v.30 no.2
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• pp.308-314
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• 2008

In this paper, we describe the fabrication of 3.5-inch QCIF active matrix organic light emitting display (AMOLED) panels driven by thin film transistors, which are produced by an ultra-low-temperature polycrystalline silicon process on plastic substrates. The over all processing scheme and technical details are discussed from the viewpoint of mechanical stability and display performance. New ideas, such as a new triple-layered metal gate structure to lower leakage current and organic layers for electrical passivation and stress reduction are highlighted. The operation of a 3.5-inch QCIF AMOLED is also demonstrated.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1071-1074
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• 2007

6Mask CMOS process in low temperature polycrystalline silicon thin film transistors (poly-Si TFTs) has been developed and verified by manufacturing a 6Mask CMOS AMLCD panel. The novel 6Mask CMOS process is realized by eliminating the storage mask, gate mask and via open mask of conventional structure.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.505-508
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• 2006

Self-heating induced device degradation and its width/length (W/L) dimension dependence were studied in p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs). Negative channel conductance was observed under high power region of output curve, which was mainly caused by hole trapping into gate oxide and also by trap state generation by self-heating effect. Self-heating effect became aggravated as W/L ratio was increased, which was understood by the differences in heat dissipation capability. By reducing applied power density normalized to TFT area, self-heating induced degradation could be reduced.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.622-625
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• 2003

The dependence of stress-induced leakage current on LTPS TFTs was characterized in this study. The impacts of poly-Si crystallization, gate insulator, impurity activation, hydrogenation process and electrostatic discharge damage were investigated. It was observed more TFTs instable characteristic under those process-assisted processes. According to the LTPS roadmap, smaller geometric and low temperature process were the future trend and the stress-induced leakage current should be worthy of remark.