• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.312-315
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• 1995

The base/gate drive suppression method proposed by Joshi and Bose is that which detects the output current polarity of the leg and, according to the polarity, suppresses the base/gate drive of one of the ore switching devices of the leg. This method has the merit that it does not have the conventional dead time problem, reduces the power loss of the driving circuit and others. But this method has difficulty in implementation. In this paper, a new base/gate drive suppression method by detecting not the output current polarity but the output voltage polarity is proposed. The proposed method is easier to implement than Joshi and Bose's method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.601-605
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• 1995

This study was concerned, after the oxide films(50 [.angs.]) were grown in a furnace and the MOS capacitor fabricated, with experimental comparison and verification about the Interference Effect of Electronic Waves in the ultra thin oxide/silicon interface. The average error was about 0.8404[%] in n'gate/p-sub and about 0.2991[%] in p$^{+}$gate/p-sub. Therefore, it was predicted that the Interference Effect of Electronic Waves can overcome somewhat according to the gate polarity.

• Korean Journal of Materials Research
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• v.24 no.3
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• pp.135-139
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• 2014

To obtain the transistor with ambipolar transfer characteristics, IGZO/SiOC thin film transistor was prepared on SiOC with various polarities as a gate insulator. The interface between a channel and insulator showed the Ohmic and Schottky contacts in the bias field of -5V ~ +5V. These contact characteristics depended on the polarities of SiOC gate insulators. The transfer characteristics of TFTs were observed the Ohmic contact on SiOC with polarity, but Schottky contact on SiOC with low polarity. The IGZO/SiOC thin film transistor with a Schottky contact in a short range bias electric field exhibited ambipolar transfer characteristics, but that with Ohmic contact in a short range electric field showed unipolar characteristics by the trapping phenomenon due to the trapped ionized defect formation.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.316-320
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• 1995

This paper proposes two base/gate drive suppression methods of NPC inverters. The first is the output current polarity detection type, which can be regarded as an extension of Joshi and Bose's method for ordinary inverters. But this method has difficulties in implementation. The second is the output voltage polarity detection type, which is easier to implement than the former. The base/gate drive suppression methods have the merit that it does not have the dead time problem, reduces the power loss of the driving circuit, and others.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.97-98
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• 2006

High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.687-690
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• 2003

Experimental results are presented for gate oxide degradation and its effect on device parameters under negative and positive bias stress conditions using NMOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both hole- and electron-trapping are found to dominate the reliability of gate oxide. However, with changing gate voltage polarity, the degradation becomes dominated by electron trapping. Statistical parameter variations as well as the "OFF" leakage current depend on those charge trapping. Our results therefore show that Si or O bond breakage by electron can be another origin of the investigated gate oxide degradation.gradation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.5
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• pp.42-47
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• 2004

This research has improved the problem of discharge AND gate PDP proposed before. The polarity of the DC discharge which composes AND gate is reversely designed and the cross talk problem to the adjacent scanning electrode has been improved. The AND gate proposed before operated by using non-linearity of the discharge by the space charge. In this research, new discharge NOT logic in which it was used that an applied voltage changed with the discharge circuit was added to AND gate. AND gate came to operate more stably. A selective address was able to be discharged with four horizontal scanning electrodes from the experiment result. The operation margin of the AND gate discharge obtained 34V and of the address discharge obtained 70V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.52-59
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• 1989

The reliability of the thin thermal oxide was investigated by using constant current stress method. Polysilicon gate MOS capacitors with oxide thickness range of 20-25nm were used in this experiment. Automatic measurement and statistical data analysis which were essential in reliability evaluation of VLSI process preformed by HP 9000 computer. Based on TDDB results, defect density, breakdown charge (Qbd) and lifetime of oxide film were evaluated. According to the polarity of the stress, some different characteristics were shown. Defect density was 62/$cm^2$ at negative gate injection. The value of Qbd was about 30C/$cm^2$ at positive gate injection, and about 21C/$cm^2$ at negative. The current density acceleration factor was 1.43$cm^2$/A for negative gate injection, and 1.25$cm^2$/A for positive gate injection.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.2
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• pp.73-77
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• 2000

A dual-gate SOI SA-LIGBT (shorted-anode lateral insulated gate bipolar transistor) which eliminates the snapback effectively is proposed and verified by numerical simulation. The elimination of the snapback in I-V characteristics is obtained by initiating the hole injection at low anode voltage by employing a dual gate and a floating electrode in the proposed device. For the proposed device, the snapback phenomenon is completely eliminate, while snapback of conventional SA-LIGBT occurs at anode voltage of 11 V. Also, the drive signals of two gates have same polarity by employing the floating electrode, thereby requiring no additional power supply.