• 한국지반신소재학회논문집
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• 제9권2호
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• pp.11-20
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• 2010

본 연구에서는 국내에서 사용하고 있는 연직배수재의 통수능시험 평가방법과 국내 관련 시방기준들을 고찰하고 연직배수재통수능 시험시 결과에 영향을 미치는 인자로 동수경사 변화에 따른연직배수재의 통수능 시험 결과를 분석하였다. 국내 연직배수재의 통수능 평가시험방법으로 기존 Delft 방법에 근거한 KS K 0940(2008)이 최근 한국표준으로 등재되었으며, 이 시험방법을 사용하는 경우 동수경사의 변화에 따라 연직배수재의 통수능의 차이가 크게 나타날 가능성이 있는 것으로 확인되었다.

• Journal of electromagnetic engineering and science
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• 제9권2호
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• pp.78-84
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• 2009

This paper represents the effects of drain bias on the linearity and efficiency of an analog pre-distortion power amplifier(PA) for wideband code division multiple access(WCDMA) repeater applications. For verification, an analog predistorter(APD) with three-branch nonlinear paths for memory-effect compensation is implemented and a class-AB PA is fabricated using a 30-W Si LOMaS. From the measured results, at an average output power of 33 dBm(lO-dB back-off power), the PA with APD shows the adjacent channel leakage ratio(ACLR, ${\pm}$5 MHz offset) of below -45.1 dBc, with a drain efficiency of 24 % at the drain bias voltage($V_{DD}$) of 18 V. This compared an ACLR of -36.7 dEc and drain efficiency of 14.1 % at the $V_{DD}$ of 28 V for a PA without APD.

• 한국전자통신학회논문지
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• 제13권5호
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• pp.959-964
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• 2018

본 논문에서는 고주파에서 동작하는 공핍형 SOI MOSFET의 드레인 전류가 유도성 기생성분에 의해서 응답지연이 일어나는 것을 처음으로 확인하였다. 공핍형 SOI MOSFET는 드레인전압 변동에 따른 드레인전류의 응답지연이 발생하기 때문에 일반적인 MOSFET 고주파모델로는 해석할 수가 없다. 이러한 응답지연은 non-quasi-static 효과로 설명될 수 있으며 SOI MOSFET에서는 일반적인 MOSFET에 비해 유도성 기생성분에 의해 응답지연이 크게 발생하게 된다. 본 논문에서 제시한 고주파모델을 이용하여 공핍형 SOI MOSFET의 드레인 응답지연을 잘 표현하는지 확인한다.

• 한국농공학회지
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• 제38권1호
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• pp.116-127
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• 1996

This paper dealt with FEM analysis of foundation improved with pack drain. The theory on pack drain was scrutinized and observed values in the field were compared with numerical results. Work site of Kwangyang container pier was selected as a ease study in which measurement of settlement and pore water pressure was accurately carried out. Biot's consolidation equation was selected as governing One, coupled with modified Camclay model as constitutive one. Christian and Boehmer's numerical technique was adopted. Behavior of foundation with pack drain is not simple but very complicated. Discontinuity resulted from rigidity difference between adjacent materials, smear effect and complicated boundary conditions should be considered in the behavior analysis of foundation behavior. The results of numerical analysis were influenced by smear zone. In relevant to this effect, finite element analysis was carried out using the reduced horizontal coefficient of permeability in the smear zone; The numerical results were compared with observed values in surface settlement. including pore water pressure. However only lateral di5plaoement by numerical ana1Ysis was shown since its measurement was not performed in the field. The predication of settlement to be developed later can be effectively employed for the obtimization of construction. The predication of residual settlement using the data measured in the field was made by Hoshino, Asaoka and hyperbolic method. Among them, the hyperbolic method proved best one. Settlements accorded well between numsrical and observed values while pore pressure showed a slight difference. Lateral displacement showed largest values at constant distance from ground surface. The validation of foundation analysis improved with pack drain by computer program employed in this study selecting modified Cam-clay model was satisfactorily secured.

• 기술사
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• 제2권8호
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• pp.33-37
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• 1969

• 대한전자공학회논문지TC
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• 제46권3호
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• pp.40-47
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• 2009

본 논문에서는 W-CDMA 기지국용 envelope tracking 전력 증폭기의 선형성 특성을 개선하는 새로운 드레인 바이어스 기법을 제안한다. 기존의 envelope tracking 전력 증폭기에서 드레인 바이어스 전압은 트랜지스터의 문턱전압 근처까지 감소하여 선형성 특성이 크게 나빠진다. 이 문제를 해결하기 위해서 본 연구에서는 입력 신호가 작을 때는 드레인 바이어스 전압이 고정된 class AB로 동작하게 하고 입력 신호가 클 때는 envelope tracking 동작을 하도록 하는 방법을 제안한다. 또한, envelope tracking 동작에서 신호의 왜곡을 줄이도록 드레인 바이어스 전압과 입력 신호의 관계를 새로이 구한다. 제안된 기법의 효과를 검증하기 위하여 class AB Si-LDMOS 전력 증폭기를 사용하여 W-CDMA envelope tracking 전력 증폭기를 설계하였다. 제안된 드레인 바이어스 기법은 평균 효율을 저하시키지 않으면서 선형성 특성을 크게 개선하여 추가의 선형화 기법 없이도 W-CDMA 기지국용 전력 증폭기의 선형성 사양을 만족시키는 것을 시뮬레이션을 통해 확인하였다.

• 대한전자공학회논문지TC
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• 제43권5호
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• pp.128-136
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• 2006

본 논문에서는 3GPP 중계기 및 기지국용 50W급 Doherty 전력증폭기를 설계 및 제작하였다. 이상적인 Doherty 전력증폭기는 효율개선과 고출력 특성이 뛰어나지만 이를 구현하기 위해서는 바이어스 조절이 어렵다. 이를 해결하고자 기존의 Gate 바이어스 조절회로를 가진 Doherty(GDCHD) 전력증폭기에 Drain 바이어스 조절회로를 첨가한 GDCHD(Gate and Drain Control Hybrid Doherty) 전력증폭기를 구현하였다. 실험결과 3GPP 동작주파수 대역인 $2.11{\sim}2.17\;GHz$에서 이득이 57.03 dB이고, PEP 출력이 50.30 dBm, W-CDMA 평균전력 47.01 dBm, 5MHz offset 주파수대역에서 -40.45 dBc의 ACLR 특성을 가졌으며, 각각의 파라미터는 설계하고자 하는 증폭기의 사양을 만족하였다. 특히 GDCHD 전력증폭기는 일반적인 Doherty 전력증폭기에 비해 ACLR에 따른 효율 개선성능이 우수하였다.

• Journal of Advanced Marine Engineering and Technology
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• 제32권8호
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2000년도 봄 학술발표회 논문집
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• pp.685-692
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• 2000

Vertical drain used improvement soft clay is made of not only decreasing construction time but also increasing the ground strength during some decades. As, it is applied to improvement soft clay with vertical drain, it is designed by the result that is caused by oedemeter test ignored anisotropic of the ground related to consolidation conditions. When we are expected consolidation conditions, the most important factors is soil of compaction and water permeability. Above all, anisotropic of the ground permeability show the results which differ between vertical and radial drainage. Recently, We study for radial consolidation coefficient and permeability coefficient that utilized Rowe Cell Consolidation and permeability tester but, it dont use well because of not only a supply lack also difficulty of test. The paper experimented with searching anisotropic of the ground so there are Rowe Cell test, standard consolidation tester and modified standard consolidation test that have pohang's soft clay ground. Therefore, we find anisotropic of the ground and a tester of easy use more than before. We made a comparison test result between the devised tester and Rowe Cell tester, Also, we learned average degree of consolidation for partial penetrating vertical drains. We were found relations as effective stress-void and effective stress-permeability coefficient through those tests.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).