• Journal of IKEEE
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• v.25 no.2
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• pp.344-349
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• 2021

This paper proposes a structure in which Trench SiO₂ is grown inside of Super Junction IGBT P-Pillar. When observing the electric field in 3D, we checked the region where the electric field have not affected inside of the P-Pillar. The pillar region's portion resistance is varied by the breakdown voltage and size of each pillar, which reduces the size by growing SiO₂ after trenching has no field effect inside of that. At 4.5kV the same breakdown voltage, it was confirmed that the On-state voltage drop improved by about 58%, 19% compared to Field Stop IGBT and conventional Super Junction IGBT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.6
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• pp.345-348
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• 2017

In this work, static characteristics of 4H-SiC SJ-ACCUFETs were obtained by adjusting the p-pillar region. The structure of this SJ-ACCUFET was designed by using a two-dimensional simulator. The static characteristics of SJ-ACCUFET, such as the breakdown voltages, on-resistance, and figure of merits, were obtained by varying the p-pillar doping concentration from $1{\times}10^{15}cm^{-3}$ to $5{\times}10^{16}cm^{-3}$ and the thickness from $0{\mu}m$ to $9{\mu}m$. The doping concentration and the thickness of p-pillar region are closely related to the break down voltage and on-resistance and threshold voltages. Hence a silicon carbide SJ-ACCUFET structure with highly intensified breakdown voltages and low on-resistances with good figure of merits can be achieved by optimizing the p-pillar thickness and doping concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.8
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• pp.497-500
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• 2014

In this paper, we analyze electrical characteristics of n/p-pillar layer according to trench angle which is the most important characteristics of SJ MOSFET and core process. Because research target is 600 V class SJ MOSFET, so conclusively trench angle deduced 89.5 degree to implement the breakdown voltage 750 V with 30% margin rate. we found that on resistance is $22mohm{\cdot}cm^2$ and threshold voltage is 3.5 V. Moreover, depletion layer of electric field distribution also uniformly distributes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.3
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• pp.173-176
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• 2020

This study focuses on a pillar in which is implanted a P-type maneuver under a P base. This structure is called a super junction structure. By inserting the pillar, the electric field concentrated on the P base is shared by the pillar, so the columns can be dispersed while maintaining a high breakdown voltage. Ten pillars were generated during the multi epitaxial process. The interval between pillars is varied to optimize the electric field to be concentrated on the pillar at a threshold voltage of 6 V, a yield voltage of 4,500 V, and an on-state voltage drop of 3.8 V. The density of the filler gradually decreased when the interval was extended by implanting a filler with the same density. The results confirmed that the size of the depletion layer between the filler and the N-epitaxy layer was reduced, and the current flowing along the N-epitaxy layer was increased. As the interval between the fillers decreased, the cost of the epitaxial process also decreased. However, it is possible to confirm the trade-off relationship that deteriorated the electrical characteristics and efficiency.

• ETRI Journal
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• v.35 no.4
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• pp.632-637
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• 2013

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p-pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p-pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n-drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

• Journal of IKEEE
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• v.23 no.3
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• pp.756-761
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• 2019

In this paper, we propose SC-SJ(Shielding Connected-Super Junction) UMOSFET structure in which p-pillars of conventional 4H-SiC Super Junction UMOSFET structures are placed under the shielding region of UMOSFET. In the case of the proposed SC-SJ UMOSFET, the p-pillar and the shielding region are coexisted so that no breakdown by the electric field occurs in the oxide film, which enables the doping concentration of the pillar to be increased. As a result, the on-resistance is lowered to improve the static characteristics of the device. Through the Sentaurus TCAD simulation, the static characteristics of proposed structure and conventional structure were compared and analyzed. The SC-SJ UMOSFET achieves a 50% reduction in on-resistance compared to the conventional structure without any change in the breakdown voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.4
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• pp.210-213
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• 2017

In this paper, we analyzed the structural design and electrical characteristics of a 3.3 kV super junction FS IGBT as a next generation power device. The device parameters were extracted by design and process simulation. To obtain optimal breakdown voltage, we researched the breakdown characteristics. Initially, we confirmed that the breakdown voltage decreased as trench depth increased. We analyzed the breakdown voltage according to p pillar dose. As a result of the experiment, we confirmed that the breakdown voltage increased as p pillar dose increased. To obtain more than 3.3 kV, the p pillar dose was $5{\times}10^{13}cm^{-2}$, and the epi layer resistance was $140{\Omega}$. We extracted design and process parameters considering the on state voltage drop.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1529_1530
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• 2009

The process conditions for fabricating p-type silicon pillars were optimized by controlling current density, bath temperature. To get best process flexibility for pillar arrays formation, three factors affecting pillar formation were changed. First, the solution bath was designed to keep constant temperature during the experiment irrespective of external temperature. Second, the counter Pt electrode was changed from rod type to mesh to obtain uniform distribution of current density. Third, Cr-Cu alloy electrode instead of Cu was used to increase electrode current density.

• Applied Microscopy
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• v.50
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• pp.17.1-17.9
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• 2020

Recent advances in fabrication have enabled radial-junction architectures for cost-effective and high-performance optoelectronic devices. Unlike a planar PN junction, a radial-junction geometry maximizes the optical interaction in the three-dimensional (3D) structures, while effectively extracting the generated carriers via the conformal PN junction. In this paper, we report characterizations of radial PN junctions that consist of p-type Si micropillars created by deep reactive-ion etching (DRIE) and an n-type layer formed by phosphorus gas diffusion. We use electron-beam induced current (EBIC) microscopy to access the 3D junction profile from the sidewall of the pillars. Our EBIC images reveal uniform PN junctions conformally constructed on the 3D pillar array. Based on Monte-Carlo simulations and EBIC modeling, we estimate local carrier separation/collection efficiency that reflects the quality of the PN junction. We find the EBIC efficiency of the pillar array increases with the incident electron beam energy, consistent with the EBIC behaviors observed in a high-quality planar PN junction. The magnitude of the EBIC efficiency of our pillar array is about 70% at 10 kV, slightly lower than that of the planar device (≈ 81%). We suggest that this reduction could be attributed to the unpassivated pillar surface and the unintended recombination centers in the pillar cores introduced during the DRIE processes. Our results support that the depth-dependent EBIC approach is ideally suitable for evaluating PN junctions formed on micro/nanostructured semiconductors with various geometry.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.593-593
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• 2013

나노패턴 제작은 차세대 초고밀도 반도체 메모리기술과 바이오칩 등 나노기술의 핵심 분야로, 나노패턴 구조를 나노-바이오 전자소자 및 반도체 산업분야에 적용할 경우 시장 선점 및 막대한 부가가치 창출 등을 통해 국가경쟁력 강화에 크게 기여할 것으로 기대된다. 하지만 대면적 패턴형성이 어려워 뿐만 아니라 $300^{\circ}$ 이상의 열처리 과정에 의한 생산성이 떨어진다. 또한 나노구조가 잘 이루어진 차원, 표면상태, 결정성, 화학적 조성을 갖도록 하는 합성 및 제조상의 어려움 때문이다. 이에 반해 자기정렬 ITO Dot 형성은 상기 기술한 1차원 나노구조형성을 하는 것에 비하여, 나노구조를 제작하기 위하여 공정이 단순하며, 비용 및 생산성 측면에서 유리 할 것으로 생각된다. 이에 본 연구는 E-beam을 이용하여 형성된 ITO 박막에 HCl solution을 이용하여 자기정렬 ITO Dot 형성 후 n-AlGaInP Vertical LED[VLED] 표면에 nano pillar의 두께에 각기 다르게 형성하였으며, 최종적으로 제작된 VLED의 전기적, 광학적 특성을 조사하였다.