• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.144-144
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• 2010

다결정 실리콘 박막트랜지스터 (poly-Si TFTs)는 벌크실리콘을 이용한 MOSFET소자에 비해 실리콘 박막의 형성이 간단하므로 대면적의 공정이 가능하며 다양한 기판위에 적용이 가능하여 LCD, OLED 등의 디스플레이 기기에 많이 이용되고 있다. 또한 poly-Si TFT는 3차원으로 적층된 소자의 제작이 가능하여 고집적의 한계를 극복할 소자로 주목받고 있다. 최근, DRAM은 캐패시터의 축소화와 구조적 공정이 한계점에 도달했으며 이를 극복하기 위하여 SOI 기판을 사용한 하나의 트랜지스터로 DRAM의 동작을 수행하는 1T-DRAM의 연구가 활발히 진행 중이다. 이러한 1T-DRAM 소자를 대면적과 다층구조의 공정이 가능한 poly-Si TFT를 이용하여 구현하면 초고집적의 메모리 소자를 제작 가능할 것이다. 따라서, 본 연구에서는 다결정 실리콘 박막트랜지스터 (poly-Si TFTs)를 이용한 1T-DRAM의 동작 특성을 연구하였다. 소자의 제작 방법으로는 200 nm의 열산화막이 성장된 p-type 실리콘 기판위에 상부실리콘으로 사용될 비정질 실리콘 박막을 LPCVD 방법으로 증착하였다. 다음으로 248 nm의 파장을 가지는 KrF 레이저를 이용한 eximer laser annealing (ELA) 공정을 통하여 결정화된 상부실리콘층에 TFT 소자를 제작하여 전기적 특성을 평가하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.513-516
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• 2010

In this work, a study is presented of the static characteristics of 4H-SiC DMOSFETs obtained by adjustment of the p-base region. The structure of this MOSFET was designed by the use of a device simulator (ATLAS, Silvaco.). The static characteristics of SiC DMOSFETs such as the blocking voltages, threshold voltages, on-resistances, and figures of merit were obtained as a function of variations in p-base doping concentration from $1\;{\times}\;10^{17}\;cm^{-3}$ to $5\;{\times}\;10^{17}\;cm^{-3}$ and doping depth from $0.5\;{\mu}m$ to $1.0\;{\mu}m$. It was found that the doping concentration and the depth of P-base region have a close relation with the blocking and threshold voltages. For that reason, silicon carbide DMOSFET structures with highly intensified blocking voltages with good figures of merit can be achieved by adjustment of the p-base depth and doping concentration.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1027-1033
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• 2013

In this work, a D-band imaging detector has been developed in a 65-nm CMOS technology for high frequency imaging application. The circuit was designed based on the resistive self-mixing of MOSFET devices. The fabricated detector exhibits a maximum responsivity of 400 V/W and minimum NEP of 100 $pW/Hz^{1/2}$ at 145 GHz. The chip size is $400{\mu}m{\times}450{\mu}m$ including the probing pads and a balun, while the core of the circuit occupies only $150{\mu}m{\times}100{\mu}m$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.63-63
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• 2009

In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to observe static DC characteristics, such as a threshold voltage ($V_{TH}$) and a figure of merit ($V_B^2/R_{SP,ON}$). To optimize the static DC characteristics, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. Design parameters are optimized using 2D numerical simulations and the 4H-SiC DMOSFET structure results in high figure of merit ($V_B^2/R_{SP,ON}$>~$340MW/cm^2$) for a power MOSFET in $V_B{\sim}1200V$ range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.367-373
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• 2001

A programmable A/D converter is designed with 8 N and P channel MOSFETs, respectively. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a 1.2 ${\mu}{\textrm}{m}$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10m Volt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, 37㎽ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.8
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• pp.637-640
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• 2009

In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.185-185
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• 2013

반도체 트랜지스터의 집적화 기술이 발달하고 소자가 나노미터 크기로 집적화 됨에 따라 문턱 전압의 변동, 높은 누설 전류, 문턱전압 이하에서의 기울기의 열화와 같은 단 채널 효과가 문제되고 있다. 이러한 문제점들은 비 휘발성 플래시 메모리에서 메모리 윈도우의 감소에 따른 retention 특성을 저하시킨다. 이중 게이트 구조의 metal-oxide-semiconductor field-effect-transistors (MOSFETs)은 이러한 단 채널 효과 중에서도 특히 문턱 전압의 변동을 억제하기 위해 제안되었다. 이중 게이트 MOSFETs는 상부 게이트와 하부 게이트 사이의 capacitive coupling을 이용하여 문턱전압의 변동의 제어가 용이하다는 장점을 가진다.기존의 플래시 메모리는 쓰기 및 지우기 (P/E) 동작, 그리고 읽기 동작이 채널 상부의 컨트롤 게이트에 의하여 이루어지며, 메모리 윈도우 및 신뢰성은 플로팅 게이트의 전하량의 변화에 크게 의존한다. 이에 따라 메모리 윈도우의 크기가 결정되고, 높은 P/E 전압이 요구되며, 터널링 산화막에 인가되는 높은 전계에 의하여 retention에서의 메모리 윈도우의 감소와 산화막의 물리적 손상을 초래하기 때문에 신뢰성 및 수명을 열화시키는 원인이 된다. 따라서 본 연구에서는, 상부 게이트 산화막과 하부 게이트 산화막 사이의 capacitive coupling 효과에 의하여 하부 게이트로 읽기 동작을 수행하면 메모리 윈도우를 크게 증폭시킬 수 있고, 이에 따라 동작 전압을 감소시킬 수 있는 이중 게이트 구조의 플래시 메모리를 제작하였다. 그 결과, capacitive coupling 효과에 의하여 크게 증폭된 메모리 윈도우를 얻을 수 있음을 확인하였고, 저전압 구동 및 신뢰성을 향상시킬 수 있음을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.7-8
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness ($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. The enhancement of effective hole mobility at the effective field of 0.1 MV/ccm was observed from 3-nm to 5-nm SOI thickness range.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.6-11
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.