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A 145 GHz Imaging Detector Based on 65-nm RFCMOS Technology

65-nm RFCMOS공정 기반 145 GHz 이미징 검출기

  • 윤대근 (고려대학교 전기전자전파공학부) ;
  • 김남형 (고려대학교 전기전자전파공학부) ;
  • 김동현 (고려대학교 전기전자전파공학부) ;
  • 이재성 (고려대학교 전기전자전파공학부)
  • Received : 2013.08.21
  • Accepted : 2013.10.18
  • Published : 2013.11.30

Abstract

In this work, a D-band imaging detector has been developed in a 65-nm CMOS technology for high frequency imaging application. The circuit was designed based on the resistive self-mixing of MOSFET devices. The fabricated detector exhibits a maximum responsivity of 400 V/W and minimum NEP of 100 $pW/Hz^{1/2}$ at 145 GHz. The chip size is $400{\mu}m{\times}450{\mu}m$ including the probing pads and a balun, while the core of the circuit occupies only $150{\mu}m{\times}100{\mu}m$.

본 논문에서는 고주파 이미징 시스템에 사용되는 D-band 이미징 검출기(imaging detector)를 65-nm CMOS 공정을 이용하여 설계 및 제작한 결과를 보인다. 검출기 회로 구조는 resistive self-mixing 원리에 기초를 두고 있다. 제작된 검출기는 145 GHz에서 400 V/W의 최대 반응도(responsivity)와 100 $pW/Hz^{1/2}$의 최소 NEP(Noise Equivalent Power)를 보였다. 제작된 회로의 크기는 측정용 패드와 밸룬을 포함하여 $400{\mu}m{\times}450{\mu}m$이며, 중심 회로의 크기는 $150{\mu}m{\times}100{\mu}m$이다.

Keywords

References

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