• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.345-345
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• 2010

1T-DRAM cell with solid phase (SPC) crystallized poly-Si thin film transistor was fabricated and electrical characteristics were evaluated. The fabricated device showed kink effect by negative back bias. Kink current is due to the floating body effect and it can be used to memory operation. Current difference between "1" state and "0" state was defined and the memory properties can be improved by using gate induced drain leakage (GIDL) current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.135-139
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• 2008

MFISFETs with platinum electrode on the $LiNbO_3$/aluminum nitride/Si(100) structures were successfully fabricated and the properties of the FETs have been discussed. $I_D-V_G$ characteristics of MFISFETs for linear region (that is, 0.1 V of the drain voltage) showed hysteresis loop with a counter-clockwise trace due to the ferroelectric nature of $LiNbO_3$ films. A memory window (i.e., threshold voltage shift) of the fabricated device was about 2[V] for a sweep from -4 to +4[V]. The estimated field-effect electron mobility and transconductance on a linear region were 530[$cm^2/V{\cdot}s$] and 0.16[mS/mm], respectively. The drain current of 27[${\mu}A$] on the "on" state was more than 3 orders of magnitude larger than that of 30[nA] on the "off" state at the same "read" gate voltage of l.5[V], which means the memory operation of the MFISFET.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.97-98
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• 2006

High current behaviors of extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOS) with double polarity source (DPS) for electrostatic discharge (ESD) protection are analyzed. Simulation based contour analyses reveal that combination of bipolar junction transistor operation and deep electron channeling induced by high electron injection gives rise to the second on-state. Therefore, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• Journal of the Korean Vacuum Society
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• v.11 no.2
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• pp.103-107
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• 2002

Metal/ferroelectric/semiconductor field effect transistors(MFSFET′s) with various gate electrodes, that are aluminum, platinum and poly-Si, using rapid thermal annealed $LiNbO_3$/Si(100) structures were fabricated and the properties of the FET′s have been discussed. The drain current of the "on" state of FET with Pt electrode was more than 3 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 1.5 V, which means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about $10^3$ s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.428-432
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• 2017

Silicon 기반 Metal-oxide-semiconductor field-effect transistor (MOSFET)의 크기가 감소함에 따라 silicon자체의 물성적 한계가 나타나고 있다. 이를 극복하고자 III-V 화합물 반도체가 채널소자로서 각광받고 있다. 본 연구에서는 III-V 화합물반도체 중 $In_xGa_{1-x}As$는 Indium 조성에 따른 전자구조 및 n-type MOSFET의 소자 특성을 본다. Indium의 조성이 증가함에 따라 subband의 개수와 간격이 증가하게 되어 Density of state가 감소하게 된다. 이로 인하여 Indium의 조성이 증가함에 따라 $In_xGa_{1-x}As$ 채널 MOSFET에서 상대적으로 Fermi level을 더 많이 상승시키게 되어 potential barrier를 얇아지게 만들며 또한 에너지에 따른 전류 밀도를 넓게 분포하도록 만든다. 이로 인하여 단채널에서는 In 조성이 증가함에 따라 direct source-to-drain tunnelling current이 증가하게 된다. 이로 인하여 In 조성의 증가에 따라 subthreshold swing과 ON-state current가 저하된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.526-532
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• 2015

We quantitatively investigated instability mechanisms under simultaneous positive gate and drain bias stress (SPGDBS) in self-aligned top-gate amorphous indium-zinc-oxide thin-film transistors. After SPGDBS ($V_{GS}=13V$and $V_{DS}=13V$), the parallel shift of the transfer curve into a negative $V_{GS}$ direction and the increase of on current were observed. In order to quantitatively analyze mechanisms of the SPGDBS-induced negative shift of threshold voltage (${\Delta}V_T$), we experimentally extracted the density-of-state, and then analyzed by comparing and combining measurement data and TCAD simulation. As results, 19% and 81% of ${\Delta}V_T$ were taken to the donor-state creation and the hole trapping, respectively. This donor-state seems to be doubly ionized oxygen vacancy ($V{_O}^{2+}$). In addition, it was also confirmed that the wider channel width corresponds with more negative ${\Delta}V_T$. It means that both the donor-state creation and hole trapping can be enhanced due to the increase in self-heating as the width becomes wider. Lastly, all analyzed results were verified by reproducing transfer curves through TCAD simulation.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1789-1791
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• 2007

We fabricated OTFT-OLED display panel by using Ag-paste for source and drains electrode of OTFTs. The OTFTs were fabricated by solution processes such as spin-coating for PVP gate dielectric and screen printing for S/D electrodes with Ag-paste, except pentacene active layer which was deposited by evaporation. The mobility was 0.024 cm2/V.sec , off state current ${\sim}10-11A$, threshold voltage 7.6 V and on/off current ratio ${\sim}105$. The panel consisted of 16 x 16 pixels and each pixel consisted of 2 OTFTs, 1 Capacitor and 1 OLED. The pixels successfully worked in terms of current magnitude supplied to OLED and the control ability of driving and switching OTFTs.

• Advances in nano research
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• v.12 no.1
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• pp.25-35
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• 2022

Within the framework of the density functional theory combined with the method of non-equilibrium Green's functions (DFT + NEGF), the features of electron transport in fullerene nanojunctions, which are «core-shell» nanoobjects made of a combination of fullerenes of different diameters C₂₀, C₈₀, C₁₈₀, placed between gold electrodes (in a nanogap), are studied. Their transmission spectra, the density of state, current-voltage characteristics and differential conductivity are determined. It was shown that in the energy range of -0.45-0.45 eV in the transmission spectrum of the "Au-C₁₈₀-Au" nanojunction appears a HOMO-LUMO gap with a width of 0.9 eV; when small-sized fullerenes C₂₀, C₈₀ are intercalation into the cavity C₁₈₀ the gap disappears, and a series of resonant structures are observed on their spectra. It has been established that distinct Coulomb steps appear on the current-voltage characteristics of the "Au-C₁₈₀-Au" nanojunction, but on the current-voltage characteristics "Au-C₈₀@C₁₈₀-Au", "Au-(C₂₀@C₈₀)@C₁₈₀-Au" these step structures are blurred due to a decrease in Coulomb energy. An increase in the number of Coulomb features on the dI/dV spectra of core-shell fullerene nanojunctions was revealed in comparison with nanojunctions based on fullerene C₆₀, which makes it possible to create high-speed single-electron devices on their basis. Models of single-electron transistors (SET) based on fullerene nanojunctions "Au-C₁₈₀-Au", "Au-C₈₀@C₁₈₀-Au" and "Au-(C₂₀@C₈₀)@C₁₈₀-Au" are considered. Their charge stability diagrams are analyzed and it is shown that SET based on C₈₀@C₁₈₀-, (C₂₀@C₈₀)@C₁₈₀- nanojunctions is output from the Coulomb blockade mode with the lowest drain-to-source voltage.