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Analysis of Instability Mechanism under Simultaneous Positive Gate and Drain Bias Stress in Self-Aligned Top-Gate Amorphous Indium-Zinc-Oxide Thin-Film Transistors

  • Kim, Jonghwa (School of Electrical Engineering, Kookmin University) ;
  • Choi, Sungju (School of Electrical Engineering, Kookmin University) ;
  • Jang, Jaeman (School of Electrical Engineering, Kookmin University) ;
  • Jang, Jun Tae (School of Electrical Engineering, Kookmin University) ;
  • Kim, Jungmok (School of Electrical Engineering, Kookmin University) ;
  • Choi, Sung-Jin (School of Electrical Engineering, Kookmin University) ;
  • Kim, Dong Myong (School of Electrical Engineering, Kookmin University) ;
  • Kim, Dae Hwan (School of Electrical Engineering, Kookmin University)
  • Received : 2015.04.20
  • Accepted : 2015.09.15
  • Published : 2015.10.30

Abstract

We quantitatively investigated instability mechanisms under simultaneous positive gate and drain bias stress (SPGDBS) in self-aligned top-gate amorphous indium-zinc-oxide thin-film transistors. After SPGDBS ($V_{GS}=13V$and $V_{DS}=13V$), the parallel shift of the transfer curve into a negative $V_{GS}$ direction and the increase of on current were observed. In order to quantitatively analyze mechanisms of the SPGDBS-induced negative shift of threshold voltage (${\Delta}V_T$), we experimentally extracted the density-of-state, and then analyzed by comparing and combining measurement data and TCAD simulation. As results, 19% and 81% of ${\Delta}V_T$ were taken to the donor-state creation and the hole trapping, respectively. This donor-state seems to be doubly ionized oxygen vacancy ($V{_O}^{2+}$). In addition, it was also confirmed that the wider channel width corresponds with more negative ${\Delta}V_T$. It means that both the donor-state creation and hole trapping can be enhanced due to the increase in self-heating as the width becomes wider. Lastly, all analyzed results were verified by reproducing transfer curves through TCAD simulation.

Keywords

References

  1. T. Kamiya et al., "Present status of amorphous In-Ga-Zn-O thin-film transistors," Sci. Technol. Adv. Mater., vol. 11, no. 4, p. 044305, Aug. 2010. https://doi.org/10.1088/1468-6996/11/4/044305
  2. T. Kamiya et al., "Device applications of transparent oxide semiconductors: Excitonic blue LED and transparent flexible TFT," J. Electroceramics, vol. 17, pp. 267-275, Dec. 2006. https://doi.org/10.1007/s10832-006-6710-9
  3. J. C. Park et al., "High performance amorphous oxide thin film transistors with self-aligned topgate structure," Tech. Dig. - Int. Electron Devices Meet. IEDM, pp. 191-194, Dec. 2009.
  4. M. Fujii et al., "Thermal Analysis of Degradation in $Ga_2O_3$ -$In_2O_3$ -ZnO Thin-Film Transistors," Jpn. J. Appl. Phys., vol. 47, no. 8R, pp. 6236-6240, Aug. 2008. https://doi.org/10.1143/JJAP.47.6236
  5. S. Urakawa et al., "Thermal analysis of amorphous oxide thin-film transistor degraded by combination of joule heating and hot carrier effect," Appl. Phys. Lett., vol. 102, p. 053506, Feb. 2013. https://doi.org/10.1063/1.4790619
  6. S. H. Choi and M. K. Han, "Effect of channel widths on negative shift of threshold voltage, including stress-induced hump phenomenon in InGaZnO thin-film transistors under high-gate and drain bias stress," Appl. Phys. Lett., vol. 100, no. 4, p. 043503, Jan. 2012. https://doi.org/10.1063/1.3679109
  7. S. M. Lee et al., "Device instability under high gate and drain biases in InGaZnO thin film transistors," IEEE Trans. Device Mater. Reliab., vol. 14, no. 1, pp. 471-476, Mar. 2014. https://doi.org/10.1109/TDMR.2013.2278990
  8. M. Fujii et al., "Experimental and Theoretical Analysis of Degradation in $Ga_2O_3$ -$In_2O_3$ -ZnO Thin-Film Transistors," Jpn. J. Appl. Phys., vol. 48, no. 4S, p. 04C091, Apr. 2009.
  9. Atlas User's Manual, Silvaco, Santa Clara, CA, 2014.
  10. S. C. Andrews et al., "Atomic-level control of the thermoelectric properties in polytypoid nanowires," Chem. Sci., vol. 2, pp. 706-714, Jan. 2011. https://doi.org/10.1039/c0sc00537a
  11. K. Watanabe and T. Asano, "Self-heating of laterally grown polycrystalline silicon thin-film transistor," Jpn. J. Appl. Phys., vol. 48, no. 3S2, p. 03B005, Mar. 2009.
  12. H. Im et al., "Effects of the defect creation on the bidirectional shift of threshold voltage with hump characteristics of InGaZnO TFTs under bias and thermal stress," Active-Matrix Flatpanel Displays and Devices, pp. 153-156, 2014.
  13. S. Lee et al., "Extraction of Subgap Density of States in Amorphous InGaZnO Thin-Film Transistors by Using Multifrequency Capacitance-Voltage Characteristics," IEEE Electron Device Lett., vol. 31, no. 3, pp. 231-233, Feb. 2010. https://doi.org/10.1109/LED.2009.2039634
  14. T. C. Fung et al., "2-D numerical simulation of high performance amorphous In-Ga-Zn-O TFTs for flat panel displays," Proc. AM-FPD '08, pp. 251-252, Jul. 2008.
  15. A. Janotti and C. G. Van de Walle. "Oxygen vacancies in ZnO," Appl. Phys. Lett., vol. 87, no. 12, p. 122102, Sep. 2005. https://doi.org/10.1063/1.2053360
  16. T. C. Chen et al., "Self-heating enhanced charge trapping effect for InGaZnO thin film transistor," Appl. Phys. Lett., vol. 101, no. 4, p. 042101, Jul. 2012. https://doi.org/10.1063/1.4733617
  17. O. K. B. Lui and P. Migliorato, "A New Generation-Recombination Model For Device Simulation Including The Poole-Frenkel Effect And Phonon-Assisted Tunneling," Solid-State Electronics, vol. 41, no. 4, pp. 575-583, 1997. https://doi.org/10.1016/S0038-1101(96)00148-7