• Title/Summary/Keyword: on-state drain current

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Device Optimization of N-Channel MOSFETs with Lateral Asymmetric Channel Doping Profiles

  • Baek, Ki-Ju;Kim, Jun-Kyu;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.15-19
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    • 2010
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

3-D Characterizing Analysis of Buried-Channel MOSFETs (매몰공핍형 MOS 트랜지스터의 3차원 특성 분석)

  • Kim, M. H.
    • Proceedings of the Optical Society of Korea Conference
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    • 2000.08a
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    • pp.162-163
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    • 2000
  • We have observed the short-channel effect, narrow-channel effect and small-geometry effect in terms of a variation of the threshold voltage. For a short-channel effect the threshold voltage was largely determined by the DIBL effect which stimulates more carrier injection in the channel by reducing the potential barrier between the source and channel. The effect becomes more significant for a shorter-channel device. However, the potential, field and current density distributions in the channel along the transverse direction showed a better uniformity for shorter-channel devices under the same voltage conditions. The uniformity of the current density distribution near the drain on the potential minimum point becomes worse with increasing the drain voltage due to the enhanced DIBL effect. This means that considerations for channel-width effect should be given due to the variation of the channel distributions for short-channel devices. For CCDs which are always operated at a pinch-off state the channel uniformity thus becomes significant since they often use a device structure with a channel length of > 4 ${\mu}{\textrm}{m}$ and a very high drain (or diffusion) voltage. (omitted)

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Interface Trap Effects on the Output Characteristics of GaN Schottky Barrier MOSFET (GaN Schottky Barrier MOSFET의 출력 전류에 대한 계면 트랩의 영향)

  • Park, Byeong-Jun;Kim, Han-Sol;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.31 no.4
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    • pp.271-277
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    • 2022
  • We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the Nit distribution using TCAD simulation. As interface trap number density (Nit) increased, the threshold voltage increased while the drain current density decreased. Under Nit=5.0×1010 cm-2 condition, the threshold voltage was 3.2 V for VDS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the Nit distribution type, there was an increase in the subthreshold swing (SS) following an increase in Nit. Under U-shaped Nit distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Qf) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

High Voltage β-Ga2O3 Power Metal-Oxide-Semiconductor Field-Effect Transistors (고전압 β-산화갈륨(β-Ga2O3) 전력 MOSFETs)

  • Mun, Jae-Kyoung;Cho, Kyujun;Chang, Woojin;Lee, Hyungseok;Bae, Sungbum;Kim, Jeongjin;Sung, Hokun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.32 no.3
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    • pp.201-206
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    • 2019
  • This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

Effect of electron-beam irradiation on leakage current of AlGaN/GaN HEMTs on sapphire

  • Oh, Seung Kyu;Song, Chi Gyun;Jang, Taehoon;Kwak, Joon Seop
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.617-621
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    • 2013
  • This study examined the effect of electron-beam (E-beam) irradiation on the electrical properties of n-GaN, AlGaN and AlGN/GaN structures on sapphire substrates. E-beam irradiation resulted in a significant decrease in the gate leakage current of the n-GaN, AlGaN and HEMT structure from $4.0{\times}10^{-4}A$, $6.5{\times}10^{-5}A$, $2.7{\times}10^{-8}A$ to $7.7{\times}10^{-5}A$, $7.7{\times}10^{-6}A$, $4.7{\times}10^{-9}A$, respectively, at a drain voltage of -10V. Furthermore, we also investigated the effect of E-beam irradiation on the AlGaN surface in AlGaN/GaN heterostructure high electron mobility transistors(HEMTs). The results showed that the maximum drain current density of the AlGaN/GaN HEMTs with E-beam irradiation was greatly improved, when compared to that of the AlGaN/GaN HEMTs without E-beam irradiation. These results strongly suggest that E-beam irradiation is a promising method to reduce leakage current of AlGaN/GaN HEMTs on sapphire through the neutralization the trap.

Characteristics of Double Polarity Source-Grounded Gate-Extended Drain NMOS Device for Electro-Static Discharge Protection of High Voltage Operating Microchip (마이크로 칩의 정전기 방지를 위한 DPS-GG-EDNMOS 소자의 특성)

  • Seo, Yong-Jin;Kim, Kil-Ho;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.97-98
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    • 2006
  • High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

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Effects of Pentacene Thickness and Source/Drain Contact Location on Performance of Penatacene TFT (펜타센 박막의 두께와 전극위치가 펜타센 TFT 성능에 미치는 영향)

  • 이명원;김광현;송정근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1001-1007
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    • 2002
  • In this paper we analyzed the effects of pentacene thickness and the location of source/drain contacts on the performance of pentacene TFT Above a certain thickness of pentacene thin film the pentacene grain was turned from the thin film phase into the bulk phase, resulting in degrading the crystallinity and then performance as well. For the top contact structure in which source/drain contacts are located above pentacene film, the contact resistance decreased comparing with the bottom contact structure. However, the leakage current in the off-state became large and then the related parameters such as on/off current ratio were deteriorated. We found that the thickness of around 300$\AA$-700$\AA$ was suitable, and that the bottom contact was more feasible for hig Performance pentacene OTFT.

Polycrystalline Silicon Thin Film Transistor Fabrication Technology (다결정 실리콘 박막 트랜지스터 제조공정 기술)

  • 이현우;전하응;우상호;김종철;박현섭;오계환
    • Journal of the Korean Vacuum Society
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    • v.1 no.1
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    • pp.212-222
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    • 1992
  • To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

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Determination of optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS device for ESD protection (고전압 정전기 보호용 DDDNMOS 소자의 더블 스냅백 방지를 위한 최적의 이온주입 조건 결정)

  • Seo, Yong-Jin
    • Journal of IKEEE
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    • v.26 no.3
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    • pp.333-340
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    • 2022
  • Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N- drift and N+ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.

Characteristic Analysis of 1200V Insulated Gate Bipolar Transistor Devices (1200V급 절연게이트 바이폴라 트랜지스터 특성 해석)

  • Kim, Sang-Cheol;Kim, Hyung-Woo;Kang, In-Ho;Joo, Sung-Jae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.212-213
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    • 2008
  • This paper describes the analysis of the device characteristics of the NPT type 1200V Insulated gate Bipolar Transistor. In case of NPT type IGBT devices, optimized n-epi layer thickness and concentration is important to obtain low on-state voltage and breakdown voltage characteristics. In this paper, we analyzed on-state and off-state characteristics of NPT type IGBT. Breakdown voltage of designed IGBT was higher than 1200V when we optimized Field Limiting Ring structures. And also, on-state voltage characteristics was shown less then 2.5V at 25A of drain current.

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