• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.369-370
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• 2007

본 논문에서는 IDLE 전송만을 수행하거나 버스접근빈도가 낮은 디폴트 마스터(Default Master)를 버스에 대한 접근빈도가 가장 높은 마스터로 재정의 하고, 버스접근빈도가 가장 높은 마스터를 찾기 위한 블록을 제작하여 추가하였다. 이 블록을 이용하여 버스에 대한 접근빈도와 데이터의 특성에 따라 디폴트 마스터를 재설정 해줄 수 있다 이로써 버스에 대한 접시간을 줄이고, 다중버스구조에서 단일버스구조와 동일한 전송이 가능하게 하여, 기존의 디폴트 마스터를 사용한 버스 구조에서 보다 효율적인 전송이 가능하다.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1225-1227
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• 1996

In this paper, we delelop 4-axis motion controller using TMS320c30 DSP chip and build a 5-axis vertical articulated robot control system. The 4-aixs controller uses a DSP, a high-speed AID and a D/A converter to implement advanced robot control algorithms. The robot control system uses VME-bus and VxWorks realtime multi-tasking operating system. We use RCCL type to implement robot languages.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.668-676
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• 2012

In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC $0.18{\mu}m$, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.7-16
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• 2007

In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.795-805
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• 2012

This paper proposes an algorithm and a hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional system, The pipelined broadcast algorithm is an algorithm which takes advantage of maximum bandwidth of communication bus. But unnecessary synchronization process are repeated, because the pipelined broadcast sends the data divided into many parts. In this paper, the MPI unit for pipeline chain algorithm based on circuit switching removing the redundancy of synchronization process was designed, the proposed architecture was evaluated by modeling it with systemC. Consequently, the performance of the proposed architecture was highly improved for broadcast communication up to 3.3 times that of systems using conventional pipelined broadcast algorithm, it can almost take advantage of the maximum bandwidth of transmission bus. Then, it was implemented with VerilogHDL, synthesized with TSMC 0.18um library and implemented into a chip. The area of synthesis results occupied 4,700 gates(2 input NAND gate) and utilization of total area is 2.4%. The proposed architecture achieves improvement in total performance of MPSoC occupying relatively small area.

• Smart Media Journal
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• v.1 no.1
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• pp.1-9
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• 2012

This Paper proposes an effective SoC hardware architecture implementing a VDP for Full HD TVs. The proposed architecture makes real time video processing possible with supporting efficient bus architecture and flexible interface. Video IP cores in the VDP are designed to provide a high quality of improved image enhancement function. The Avalon interface is adopted to guarantee real-time capability to IPs as well as SoC integration. This leads to reduced design time and also enhanced designer's convenience due to the easiness in IP addition, deletion, and revision for IP verification and SoC integration. The embedded software makes it possible to implement flexible real-time system by controlling setting parameter details and data transmitting schemes in real-time. The proposed VDP SoC design is implemented on Cyclon III SoPC platform. The experimental results show that our proposed architecture of the VDP SoC successfully provides required quality of Video image by converting SD level input to Full HD level image.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.103-110
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• 2014

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.