A Design of Security SoC Prototype Based on Cortex-M0

Cortex-M0 기반의 보안 SoC 프로토타입 설계

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

마이크로프로세서에 블록암호 크립토 코어를 인터페이스한 보안 SoC (System-on-Chip) 프로토타입 구현에 대해 기술한다. 마이크로프로세서로 Cortex-M0를 사용하였고, ARIA와 AES를 단일 하드웨어에 통합하여 구현한 크립토 코어가 IP로 사용되었다. 통합 ARIA-AES 크립토 코어는 ECB, CBC, CFB, CTR, OFB의 5가지 운영모드와 128-비트, 256-비트의 두 가지 마스터키 길이를 지원한다. 통합 ARIA-AES 크립토 코어를 Cortex-M0의 AHB-light 버스 프로토콜에 맞게 동작하도록 인터페이스 하였으며, 보안 SoC 프로토타입은 BFM 시뮬레이션 검증 후, FPGA 디바이스에 구현하여 하드웨어-소프트웨어 통합검증을 하였다.