• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.461-464
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• 1999

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$ to 814$\AA$ with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ . The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.17-20
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• 2002

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4A to 814A with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ The oxide charge state of traps generated by the stress high voltage contain either a positive or negative charge.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.249-254
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• 2015

Solution-derived amorphous indium-gallium-zinc oxide (a-IGZO) thin-film-transistor (TFTs) were developed using a microwave irradiation treatment at low process temperature below $300^{\circ}C$. Compared to conventional furnace-annealing, the a-IGZO TFTs annealed by microwave irradiation exhibited better electrical characteristics in terms of field effect mobility, SS, and on/off current ratio, although the annealing temperature of microwave irradiation is much lower than that of furnace annealing. The microwave irradiated TFTs showed a smaller $V_{th}$ shift under the positive gate bias stress (PGBS) and negative gate bias stress (NGBS) tests owing to a lower ratio of oxygen vacancies, surface absorbed oxygen molecules, and reduced interface trapping in a-IGZO. Therefore, microwave irradiation is very promising to low-temperature process.

• Transactions on Electrical and Electronic Materials
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• v.18 no.3
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• pp.141-143
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• 2017

Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at $500^{\circ}C$. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from $14.77cm^2/Vs$ to $35.59cm^2/Vs$ simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.

• Current Applied Physics
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• v.18 no.11
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• pp.1447-1450
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• 2018

The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage ($V_{th}$) distribution of the IGZO thin film transistors. The total BTS ${\Delta}V_{th}$ and the $V_{th}$ distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict $V_{th}$ instability of IGZO TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1701-1703
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• 2006

Here we describe a novel driving scheme in the form of negative AC bias stress (NAC) to compensate shift in the threshold voltage for hydrogenated amorphous silicon (${\alpha}$-Si:H) thin film transistor (TFT) for AMOLED applications. This scheme preserves the threshold voltage shift of ${\alpha}$-Si:H TFT for infinitely long duration of time(>30,000 hours) and thereby overall performance, without using any additional TFTs for compensation. We briefly describe about the possible driving schemes in order to implement for real time AMOLED applications. We attribute most of the results based on concept of plugging holes and electrons across the interface of the gate insulator in a controlled manner.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.231.2-231.2
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• 2014

훌륭한 전기적 특성을 갖는 ZnO 기반의 산화물 반도체 박막트랜지스터(TFT)는 AMOLEDs에 적용될 수 있다. 하지만 이러한 장점에도 불구하고 산화물 반도체 TFT소자에 전압이 인가되었을 때 문턱 전압이 이동하게 되는 안정성 문제를 갖는다. 따라서 이를 해결하기 위한 연구가 널리 진행 되고 있다. 본 연구소에서는 고압 분위기 열처리를 통해 안정성의 원인으로 작용할 수 있는 산소공공(Oxygen vacancy)을 감소시키는 연구를 진행하였다. 산화물 반도체 TFT소자의 안정성을 향상시키는 대표적인 분위기 열처리로는 산소 고압 열처리(HPA)가 있으며, 또한 H2O 기체를 사용한 열처리를 통해 TFT소자의 안정성을 높일 수 있다는 연구 결과가 보고된 바 있다. 본 연구에서는 IGZO TFT소자에 H2O보다 더 큰 반응성을 갖는 산화제인 H2O2 기체를 사용한 HPA를 통해 positive bias stress(PBS) 및 negative bias illumination stress(NBIS) 조건에서 안정성이 향상됨을 확인하였고 이를 H2O 기체를 사용한 경우와 비교하였다. 그 결과 H2O2 기체를 산화제로 사용할 때 기존 H2O 기체에 비해 효과적인 PBS 및 NBIS 신뢰성 개선을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.26-34
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• 1997

To develop ultrathin gate oxide for ULSI MOSFETs, for the first time, we fabricated MOS capacitors with 65.angs. thick initial oxide grown by high pressure oxidation (HIPOX) at 700.deg. C in 5 atmosphere $O_{2}$ ambient and then followed by rapid thermal nitridation (RTN) in N$_{2}$O ambient. The dielectric breakdown fields of the initial HIPOX oxide are 13.0 MV/cm and 13.8MV/cm for negative and positive gate bias, respectively and are dependent on nitridation temeprature and time.The lifetimes of the HIPOX oxides extractd by TDDB method are 1.1*10$^{8}$ sec and 3.4 * 10$^{9}$ sec for negative and positive stress current, respectively. The lifetime of the HIPOX oxide dfor negative stress current increases with nitridation time in N$_{2}$O ambient at 1100.deg.C, reaching maximum value stress curretn increases with nitridation time in N$_{2}$O ambient at 1100.deg. C reacing maximum value of 1.2*10$^{9}$ sec for 30 sec of nitridation time, and then subsequently decreases at the longer nitridation time. The lifetimes of the nitrided-HIPOX oxides are longer than 10 years when nitridations are carried out longer than about 50 sec and 12 sec at 1000.deg. C, and 1100.deg. C, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.24-28
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• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.687-690
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• 2003

Experimental results are presented for gate oxide degradation and its effect on device parameters under negative and positive bias stress conditions using NMOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both hole- and electron-trapping are found to dominate the reliability of gate oxide. However, with changing gate voltage polarity, the degradation becomes dominated by electron trapping. Statistical parameter variations as well as the "OFF" leakage current depend on those charge trapping. Our results therefore show that Si or O bond breakage by electron can be another origin of the investigated gate oxide degradation.gradation.