• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.33-33
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• 2009

Silicon nano-structures have great potential in bionic sensor applications. Atomic force microscopy (AFM) anodic oxidation have many advantages for the nanostructure fabrication, such as simple process in atmosphere at room temperature, compatibility with conventional Si process. In this work, we fabricated simple FET structures with channel width W~ 10nm (nanowire) and $1{\mu}m$ (nano-ribbon) on ~10, 20 and 100nm-thinned silicon-on-insulator (SOI) wafers in order to investigate the surface effect on the transport characteristics of nano-channel. For further quantitative analysis, we carried out the 2D numerical simulations to investigate the effect of channel surface states on the carrier distribution behavior inside the channel. The simulated 2D cross-sectional structures of fabricated devices had channel heights of H ~ 10, 20, and 100nm, widths of L ~ $1{\mu}m$ and 10nm respectively, where we simultaneously varied the channel surface charge density from $1{\times}10^{-9}$ to $1{\times}10^{-7}C/cm2$. It has been shown that the side-wall charge of nanowire channel mainly affect the I-V characteristics and this was confirmed by the 2D numerical simulations.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.39-45
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• 2016

In this paper, prcess modeling of germanium condensation has been performed and a germanium PMOSFET having nanowire channel implented by the condensation process has been designed and characterized by device simulations. Based on the previous experimental results, our modeling results demonstrate that the ratio of germanium concentration at the silicon germanium-silicon dioxide interface ($C_S$) to that in the bulk region ($C_B$) which are obtainable during the germanium condensation is approximately 4.03 and the effective diffusion coefficient ($D_{eff}$) of germanium atom is $3.16nm^2/s$. Furthermore, a germanium nanowire-channel PMOSFET having the ultra-thin germanium channel on the silicon core that can be fabricated by the germanium condensation has been designed and characterized. As the result, it is confirmed that the proposed device having the coaxial nanowire consisting of silicon core and germanium channel might have superior performances over the device with either all-silicon or all-germanium channel.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.77-78
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• 2009

We report numerical simulations to investigate of the dependence of the on/off current ratio and channel charge distributions in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width and thicknesses. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L of 10um, but varying the channel width W from 5nm to 5um, and thickness t from 10nm to 30nm. We have shown that $Q_{ON}/Q_{OFF}$ drastically decreases (from ${\sim}2.9{\times}10^4$ to ${\sim}9.8{\times}10^3$) as the channel thickness increases (from 10nm to 30nm). As a result of the simulation using a quantum model, even higher charge density in the bottom of SiNW channel was observed than that in the bottom of control channel.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.357-364
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• 2015

In this work, we investigate the quantum effects exhibited from ultra-thin GAA(gate-all-around) Nanowire FETs for Sub 14nm Technology. We face designing challenges particularly short channel effects (SCE). However traditional MOSFET SCE models become invalid due to unexpected quantum effects. In this paper, we investigated various performance factors of the GAA Nanowire FET structure, which is promising future device. We observe a variety of quantum effects that are not seen when large scale. Such are source drain tunneling due to short channel lengths, drastic threshold voltage increase caused by quantum confinement for small channel area, leakage current through thin gate oxide by tunneling, induced source barrier lowering by fringing field from drain enhanced by high k dielectric, and lastly the I-V characteristic dependence on channel materials and transport orientations owing to quantum confinement and valley splitting. Understanding these quantum phenomena will guide to reducing SCEs for future sub 14nm devices.

• ETRI Journal
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• v.41 no.6
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• Journal of Electrical Engineering and Technology
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• v.3 no.4
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• pp.566-570
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• 2008

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.361-366
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• 2013

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.266-268
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• 2013

In this paper, we study the channel doping concentration characteristics of junctionless nanowire transistors (JLT) using Edison nanowire FET device simulation. JLT has no junctions by very simple fabrication process. And this device has less variability and better electrical properties than classical inversion-mode transistors with PN junctions at the source and drain. In this simulation we use tri-gate structure. Source and drain doping concentration is $10^{20}atoms/cm^3$. The simulation results show that I-V characteristics of JLT change due to the variation of channel doping concentration.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.10
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• pp.1494-1498
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• 2017

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.