• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.10
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• pp.613-617
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• 2014

This paper was analyzed electrical characteristics of super junction power MOSFET considering to charge imbalance. We extracted optimal design and process parameter at -15% of charge imbalance. Considering extracted design and process parameters, we fabricated super junction MOSFET and analyzed electrical characteristics. We obtained 600~650 V breakdown voltage, $224{\sim}240m{\Omega}$ on resistance. This paper was showed superior on resistance of super junction MOSFET. We can use for automobile industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.32-38
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• 2003

This works reports the measurement and analysis results on the hot electron induced device degradation in Gate-All-Around SOI MOSFET's, which were fabricated using commercially available SIMOX material. It is observed that the worst-case condition of the device degradation in nMOSFETs is $V_{GS}$ = $V_{TH}$ due to the higher impact ionization rate when the parasitic bipolar transistor action is activated. It is confirmed that the device degradation is caused by the interface state generation from the extracted degradation rate and the dynamic transconductance measurement. The drain current degradation with the stress gate voltages shows that the device degradation of pMOSFETs is dominantly governed by the trapping of hot electrons, which are generated in drain avalanche hot carrier phenomena.r phenomena.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.274-281
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• 2005

A new resonant pulse converter for energy harvesting is proposed. The converter transfers energy from a low-voltage AC current to a battery. The low-voltage AC current source is an equivalent of the piezoelectric generator, which converts the mechanical energy to the electric energy. The converter consists of a full-bridge rectifier having four N-type MOSFETs and a boost converter haying N-type MOSFET and P-type MOSFET instead of diode. Switching of MOSFETs utilizes the capability of the $3^{rd}$ regional operation. The operational principles and switching method for the power control of the converter are investigated with the consideration of effects of the parasitic capacitances of MOSFETs. Simulation and experiment are performed to prove the analysis of the converter operation and to show the possibility of the $\mu$W energy harvesting.

• Transactions on Electrical and Electronic Materials
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• v.12 no.2
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• pp.43-50
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• 2011

Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio ($I_{on}/I_{off}$). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.363-366
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• 1998

25.deg. C 에서 120.deg. C까지 온도를 증가시키면서 hot carrier effect에 의한 nMOSFET의 degradation을 drain current와 transconductance의 변화를 통해 알아보았다. 온도가 증가할수록 hot carrier에 의한 degradation 이 전체적으로 줄어드는 것을 볼수 있었다. stress를 가한 후 reverse mode로 측정하였는데 saturation 영역보다 linear 영역에서 drain current의 degradation이 크게 나탔으며 온도가 증가할수록 이러한 경향이 유지되면서 degradation이 감소하였다. transconductance는 linear 영역과 saturation 영역에서 각각 측정하였는데 온도가 증가할수록 linear 영역의 degradation이 더많이 감소하였다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.707-710
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• 2003

10nm 이하의 두께를 갖는 얇은 SOI 층 위에서 우수한 동작 특성을 보이는 Fully-Depleted SOI nMOSFET 을 제작하였다. 게이트의 길이가 큰 경우에는 SOI 층이 얇지 않아도 좋은 특성을 보이지만, 게이트 길이가 100nm 이하에서는 Short Channel Effect 에 의한 특성 열화 때문에 SOI thin body 의 두께가 게이트 길이에 따라 같이 얇아져야 한다. [1] 100nm 게이트 길이 SOI-NMOSFET에서 10nm 이하 body 두께에 따라 Vth는 조금 상승했고, Subthreshold slope은 조금 개선되는 특성을 보였다. 또한, 45nm 게이트 길이와 3nm 로 추정되는 body 두께를 갖는 nMOSFET 에서 우수한 I-V 동작 특성을 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.187-194
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• 2005

An analysis of the 1/f or flicker noise in FD n-channel Double Gate SOI MOSFET is proposed. In this paper, the variation of power spectral density (PSD) of the equivalent noise voltage and noise current with respect to frequency, channel length and gate-to-source voltage at various temperatures and exponent $C(i.e\;1/f^c$ is reported. The temperature is varied 125 K from to room temperature. The variation of PSD with respect to channel length down to $0.1{\mu}m$ technology is considered. It is analyzed that l/f noise in FD n-channel Double Gate SOI MOSFET is due to both carrierdensity fluctuations and mobility-fluctuations. But controversy still exits to its origin.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.317-320
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• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.1-8
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• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.