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N-Type Carbon-Nanotube MOSFET Device Profile Optimization for Very Large Scale Integration

  • Sun, Yanan (Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay) ;
  • Kursun, Volkan (Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay)
  • Published : 2011.04.25

Abstract

Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio ($I_{on}/I_{off}$). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.

Keywords

References

  1. P. Avouris, Z. Chen, and V. Perebeinos, Nature Nanotechnol. 2, 605 (2007) [DOI: 10.1038/nnano.2007.300].
  2. J. Guo, A. Javey, H. Dai, S. Datta, and M. Lundstrom, Predicted performance advantages of carbon nanotube transistors with doped nanotubes as source/drain (2003). Available from: http://arxiv.org/abs/cond-mat/0309039.
  3. J. Guo, A. Javey, H. Dai, and M. Lundstrom, IEEE International Electron Devices Meeting (San Francisco, CA 2004) p. 703.
  4. A. Javey, J. Guo, D. B. Farmer, Q. Wang, E. Yenilmez, R. G. Gordon, M. Lundstrom, and H. Dai, Nano Lett. 4, 1319 (2004) [DOI: 10.1021/nl049222b].
  5. A. Javey, J. Guo, D. B. Farmer, Q. Wang, D. Wang, R. G. Gordon, M. Lundstrom, and H. Dai, Nano Lett. 4, 447 (2004) [DOI: 10.1021/nl035185x].
  6. A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon, and H. Dai, Nano Lett. 5, 345 (2005) [DOI: 10.1021/nl047931j].
  7. S. Lin, Y. B. Kim, and F. Lombardi, IEEE Trans. Nanotechnol. 9, 30 (2010) [DOI: 10.1109/tnano.2009.2025128].
  8. M. Moradinasab, F. Karbassian, and M. Fathipour, 1st Asia Symposium on Quality Electronic Design (Kuala Lumpur 2009) p. 19.
  9. B. Ebrahimi and A. Afzali-Kusha, 1st Asia Symposium on Quality Electronic Design (Kuala Lumpur 2009) p. 14.
  10. Y. B. Kim, F. Lombardi, and Y. J. Lee, International SoC Design Conference (Busan, Korea 2008) p. I176.
  11. S. Lin, Y. B. Kim, and F. Lombardi, 52nd IEEE International Midwest Symposium on Circuits and Systems (Cancun 2009) p. 435.
  12. Stanford University Nanoeletronics Group. Stanford University CNFET Model. Available: http://nano.stanford.edu/model.php?id=23.
  13. Y. Sun and V. Kursun, International SoC Design Conference (Incheon, Korea 2010) p. 260.
  14. R. Saito, G. Dresselhaus, and M. S. Dresselhaus, Physical Properties of Carbon Nanotubes (Imperial College Press, London, 1998).
  15. The MOSIS Service. MOSIS Scalable CMOS (SCMOS). Available: http://www.mosis.com/Technical/Designrules/scmos/scmosmain.html.
  16. J. Deng and H. S. P. Wong, IEEE Trans. Electron Devices 54, 3186 (2007) [DOI: 10.1109/ted.2007.909030].
  17. C. Kshirsagar, H. Li, T. E. Kopley, and K. Banerjee, IEEE Electron Device Lett. 29, 1408 (2008) [DOI: 10.1109/led.2008.2007598].
  18. A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. McIntyre, P. McEuen, M. Lundstrom, and H. Dai, Nature Mater. 1, 241 (2002) [DOI: 10.1038/nmat769].
  19. Y. Lu, S. Bangsaruntip, X. Wang, L. Zhang, Y. Nishi, and H. Dai, J. Am. Chem. Soc. 128, 3518 (2006) [DOI: 10.1021/ja058836v].
  20. B. Black, M. Annavaram, N. Brekelbaum, J. Devale, J. Lei, G. H. Loh, D. McCauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, S. John, and C. Webb, 39th Annual IEEE/ACM International Symposium on Microarchitecture (Orlando, FL 2006) p. 469-479.
  21. J. Deng and H. S. P. Wong, IEEE Trans. Electron Devices 54, 3195 (2007) [DOI: 10.1109/ted.2007.909043].

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