• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.351-354
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• 1998

In this paper, electrical characteristics of an n-channel Si MOSFET with L$_{s}$=0.6.mu.m under optical illumination are charaterized on wafer. Energetic photons with .gamma.=830nm, hv=1.494eV, P$_{opt}$=300mW are injected near the drain junction, the most photoresponsive region in the device, via optical fiber. We observed significantly increased drain current and transconductance, which is considered to be useful for the implementation of OEICs on silicon substrate, under optical control with P$_{opt}$=300mW. Optical power-dependent physical mechanisms responsible for the variation of electrical characteristics under optical input are also reported.d.d.d.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.559-563
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• 2002

A threshold voltage model of SiC N-channel MOSFETs for high-temperature and hard radiation environments has been developed and verified by comparing with experimental results. The proposed model includes the difference in the work functions, the surface potential, depletion charges and SiC/$SiO_2$acceptor-like interface state charges as a function of temperature. Simulations of the model shoved that interface slates were the most dominant factor for the threshold voltage decrease as the temperature increase. To verify the model, SiC N-chnnel MOSFETS were fabricated and threshold voltages as a function of temperature were measured and compared wish model simulations. From these comparisons, extracted density of interface slates was $4{\times}10^{12}\textrm{cm}^{-2}eV^{-1}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.268-270
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• 2002

For analysis of semiconductor's electrons transmission characteristics, Impact ionization(I.I.) is very important. I.I. are generation process of electron-hole pairs. Therefore, the characteristics of device can change along with applied voltage or temperature. In this paper, we are scaled down the gate length to 50nm. Also, using TCAD simulator, we are analyzed I.I. and breakdown about three models-Van Overstraeten , Okuto and Ours models.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.8
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• pp.587-595
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• 1998

Transient thermal analysis simulations are carried out using a modeling program to understand the human body model HBM ESD. The devices were simulated a one-dimensional device subjected to ESD stress by solving Poison's equation, the continuity equation, and heat flow equation. A ramp rise with peak ESD voltage during rise time is applied to the device under test and then discharged exponentially through the device. LDD and NMOS structures were studied to evaluate ESD performance, snap back voltages, device heating. Junction heating results in the necessity for increased electron concentration in the space charge region to carry the current by the ESD HBM circuit. The doping profile adihacent to junction determines the amount of charge density and magnitude of the electric field, potential drop, and device heating. Shallow slopes of LDD tend to collect the negative charge and higher potential drops and device heating.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.538-542
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• 1999

New methodology of parameter calibration is proposed for TCAD simulation of nMOSFET in ESD(Electro-Static Discharge) protection circuits. Recently, TLP(Transmission Line Pulsing) measurement has received great interest due to the ability of analyzing device characteristics when ESD pulse is applied to the ESD pulse is applied to the ESD protection circuits. This paper describes new methodology of analyizing TLP measurement, TCAD simulation, and parameter calibration.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.357-361
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• 2016

Si와 InAs 두 가지 채널 물질을 가지고 3가지 수송 방향 <100>, <110>, <111>으로 변화시키며 각각의 Nanowire nMOSFETs을 가지고 ballistic quantum transport simulation을 진행하였다. 각각의 경우에 대해 E-k curve를 구한 다음에 band curvature로 캐리어의 유효질량을 계산하고, 이를 통해 MOSFET의 전류 세기를 결정짓는 DOS와 carrier injection velocity를 구하여 어떤 경우에 가장 높은 ON-current를 흐르게 하는지 확인해 보았다. 하지만 예상과 달리 나노와이어의 직경이 1.4nm으로 매우 작기 때문에 valley-splitting이 일어나 Si<110>의 경우에 가장 작은 캐리어 유효 질량을 갖고 있는 사실을 확인할 수 있었다. 결론적으로 Si<100>의 경우에 trade-off 관계에 있는 DOS와 carrier injection velocity가 6가지 경우 중 최적의 조합을 가짐으로써 가장 높은 ON-current를 흐르게 하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.34-41
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• 1984

MOEN/MO double layer which is to be used It)r the RMOS (refractory metal oxide semiconductor) gate material has been fabricated by means of low temperature reactive sputtering in N2 and Ar mixture. Good Mo2N film was obtained in the volumetric mixture of Ar:N2=95:5. The sheet resistance of the fabricated Mo7N film was about 1.20 - 1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film, and this would enable to improve the operational speed of devices fabricated with this material. When PSG (phosphorus silicate glass) was used as impurity diffusion source for the source and drain of the RMOSFET in the N2 atmosphere at about 110$0^{\circ}C$, the Mo2N was reduced to Mo resulting in much smaller sheet resistance of about 0.38 ohm/square. The threshold voltage of the RMOSFET fabricated in our experiment was - 1.5 V, and both depletion and enhancement mode RMOSFETs could be obtained.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.10
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• pp.767-770
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• 2010

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.82-90
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• 1995

We proposed SAW (Self-Algined Selectively Grown W-Gate) MOSFET structure, and strudied electrical characteristics of the fabricated SAW MOSFETs. The threshold volgate of 0.21${\mu}$m SAW NMOSFET was 0.18 V and that of 0.24 ${\mu}$m SAW PMOSFET was -0.16 V. The subthreshold slope was 74 mV/decade for NMOSFET and 82 mV/decade for PMOSFET. The maximum transconductance of NMOSFET and PMOSFET, at V$_{GS}$=2.5 V and V$_{DS}$=1.5 V, were260 mS/mm and 122 mS/mm. The measured saturation drain current at V$_{GS}$=V$_{DS}$ =2.5 V was 0.574 mA/${\mu}$m for NMOSFET and -0.228 mA/${\mu}$m for PMOSFET. The gate resistance of SAW MOSFET was about m$\Omega$cm and the n+-p junction capacitance of SAW MOSFET was about 10% lowas than that of the conventional MOSFET's.