• 제목/요약/키워드: multi-time programmable

검색결과 55건 처리시간 0.019초

PMIC용 저면적 64비트 MTP IP 설계 (Design of a 64b Multi-Time Programmable Memory IP for PMICs)

  • 최대용;김일준;하판봉;김영희
    • 한국정보전자통신기술학회논문지
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    • 제9권4호
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    • pp.419-427
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    • 2016
  • 본 논문에서는 저면적 64bit MTP IP를 설계하였다. 저면적 설계기술로는 MTP cell의 inhibit voltage를 기존의 VPP/3과 VNN/3 전압 대신 모두 0V를 사용하므로 VPPL(=VPP/3) regulator 회로와 VNNL(VNN/3) charge pump 회로를 제거하였다. 그리고 external pad를 이용하여 VPP program voltage를 forcing하므로 VPP charge pump 회로를 제거하였다. 또한 VNN charge pump는 VPP 전압을 이용하여 1-stage negative charge pump 회로로 pumping해서 -VPP의 전압을 공급하도록 설계를 하였다. 설계된 64bit MTP IP size는 $377.585{\mu}m{\times}328.265{\mu}m$(=0.124mm2)이며, DC-DC converter관련 layout size는 기존의 회로 대비 76.4%를 줄였다.

PMIC용 512비트 MTP 메모리 IP설계 (Design of a 512b Multi-Time Programmable Memory IPs for PMICs)

  • 장지혜;하판봉;김영희
    • 한국정보전자통신기술학회논문지
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    • 제9권1호
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    • pp.120-131
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    • 2016
  • 본 논문에서는 back-gate bias 전압인 VNN (Negative Voltage)을 이용하여 5V의 MV (Medium Voltage) 소자만 이용하여 FN (Fowler-Nordheim) tunneling 방식으로 write하는 MTP cell을 사용하여 512비트 MTP IP를 설계하였다. 사용된 MTP cell은 CG(Control Gate) capacitor, TG(Tunnel Gate) transistor와 select transistor로 구성되어 있다. MTP cell size를 줄이기 위해 TG transistor와 select transistor를 위한 PW(P-Well)과 CG capacitor를 위한 PW 2개만 사용하였으며, DNW(Deep N-Well)은 512bit MTP cell array에 하나만 사용하였다. 512비트 MTP IP 설계에서는 BGR을 이용한 voltage regulator에 의해 regulation된 V1V (=1V)의 전압을 이용하여 VPP와 VNN level detector를 설계하므로 PVT variation에 둔감한 ${\pm}8V$의 pumping 전압을 공급할 수 있는 VPP와 VNN 발생회로를 제안하였다.

BCD 공정 기반 저면적 MTP 설계 (Design of Small-Area MTP Memory Based on a BCD Process)

  • 권순우;리룡화;김도훈;하판봉;김영희
    • 전기전자학회논문지
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    • 제28권1호
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    • pp.78-89
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    • 2024
  • 차량용 반도체에서 사용되는 BCD 공정 기반의 PMIC 칩은 아날로그 회로를 트리밍하기 위해 추가 마스크가 필요없는 MTP(Multi-Time Programmable) IP(Intellectual Property)를 요구한다. 본 논문에서는 저면적 MTP IP 설계를 위해 2개의 트랜지스터와 1개의 MOS 커패시터를 갖는 single poly EEPROM 셀인 MTP 셀에서 NCAP(NMOS Capacitor) 대신 PCAP(PMOS Capacitor)을 사용한 MTP 셀을 사용하여 MTP 셀 사이즈를 18.4% 정도 줄였다. 그리고 MTP IP 회로 설계 관점에서 MTP IP 설계의 CG 구동회로와 TG 구동회로에 2-stage voltage shifter 회로를 적용하였고, DC-DC 변환기 회로의 면적을 줄이기 위해 전하 펌핑 방식을 사용하는 VPP(=7.75V), VNN(=-7.75V)와 VNNL(=-2.5V) 전하 펌프 회로에서 각각의 전하 펌프마다 별도로 두고 있는 ring oscillator 회로를 하나만 둔 회로를 제안하였으며, VPPL(=2.5V)은 전하펌프 대신 voltage regulator 회로를 사용하는 방식을 제안하였다. 180nm BCD 공정 기반으로 설계된 4Kb MTP IP 사이즈는 0.493mm2이다.

A multi-radio sink node designed for wireless SHM applications

  • Yuan, Shenfang;Wang, Zilong;Qiu, Lei;Wang, Yang;Liu, Menglong
    • Smart Structures and Systems
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    • 제11권3호
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    • pp.261-282
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    • 2013
  • Structural health monitoring (SHM) is an application area of Wireless Sensor Networks (WSNs) which usually needs high data communication rate to transfer a large amount of monitoring data. Traditional sink node can only process data from one communication channel at the same time because of the single radio chip structure. The sink node constitutes a bottleneck for constructing a high data rate SHM application giving rise to a long data transfer time. Multi-channel communication has been proved to be an efficient method to improve the data throughput by enabling parallel transmissions among different frequency channels. This paper proposes an 8-radio integrated sink node design method based on Field Programmable Gate Array (FPGA) and the time synchronization mechanism for the multi-channel network based on the proposed sink node. Three experiments have been performed to evaluate the data transfer ability of the developed multi-radio sink node and the performance of the time synchronization mechanism. A high data throughput of 1020Kbps of the developed sink node has been proved by experiments using IEEE.805.15.4.

Linearity improvement of UltraScale+ FPGA-based time-to-digital converter

  • Jaewon Kim;Jin Ho Jung;Yong Choi;Jiwoong Jung;Sangwon Lee
    • Nuclear Engineering and Technology
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    • 제55권2호
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    • pp.484-492
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    • 2023
  • Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

저가형 요분석 시스템의 다중 광 검출 모듈개발 (Development of multi-colorimeter module for low-cost urinalysis strip readers)

  • 예수영;전용욱;정도운;전계록;노정훈
    • 센서학회지
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    • 제17권5호
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    • pp.387-395
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    • 2008
  • An optic module system is developed adopting multiple colorimetry units for the measurement of multi-pad urinalysis dipsticks. Multiple photometry system instead of moving mechanisms has the advantages of system reliability and simplicity as well as economic aspects due to the recent development of economic color light emitting diodes and stable photo sensors. An integration amplifier with programmable integration time, a current source circuit with selectable and stable current settings were connected through analog multiplexers to thirty light emitting diodes for illumination and ten photo transistors for reading each strip pad. All the circuits are controlled by a microprocessor through a simple set of serial communication commands. The detect ability is eighteen times better than the minimum color difference of the test grading which is 0.013 in urobilinogen in the color space defined in this paper.

Hardware Implementation for Real-Time Speech Processing with Multiple Microphones

  • Seok, Cheong-Gyu;Choi, Jong-Suk;Kim, Mun-Sang;Park, Gwi-Tea
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2005년도 ICCAS
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    • pp.215-220
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    • 2005
  • Nowadays, various speech processing systems are being introduced in the fields of robotics. However, real-time processing and high performances are required to properly implement speech processing system for the autonomous robots. Achieving these goals requires advanced hardware techniques including intelligent software algorithms. For example, we need nonlinear amplifier boards which are able to adjust the compression radio (CR) via computer programming. And the necessity for noise reduction, double-buffering on EPLD (Erasable programmable logic device), simultaneous multi-channel AD conversion, distant sound localization will be explained in this paper. These ideas can be used to improve distant and omni-directional speech recognition. This speech processing system, based on embedded Linux system, is supposed to be mounted on the new home service robot, which is being developed at KIST (Korea Institute of Science and Technology)

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다중모터 제어를 위한 SVPWM 모듈의 구현 (Implementation of SVPWM Module for the Multi-Motor Control)

  • 하동현;현동석
    • 조명전기설비학회논문지
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    • 제23권9호
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    • pp.124-129
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    • 2009
  • 최근 자동차 및 자동화 등 많은 첨단 산업분야에서 산업용 모터 정밀 제어를 위한 인버터의 요구가 증가하고 있다. 본 논문에서는 FPGA를 이용하여 단일 제어 유닛으로 여러 개의 모터를 제어할 수 있는 SVPWM 모듈을 설계 제작하여 모터 정밀제어에 응용하고자 한다. 개발된 WVPWM 모듈에는 PWM 발생기뿐만 아니라 위치 및 전류센서 처리 부분과 데프타임 보상기 알고리즘도 함께 구현되었다. 개발 툴은 ALTERA Quartus 8.0을 사용하였으며 시뮬레이션에 의해 동작 특성을 검증하였고 실험을 통해 성능을 검증하였다.

System Strategies for Time-Domain Emission Measurements above 1 GHz

  • Hoffmann, Christian;Slim, Hassan Hani;Russer, Peter
    • Journal of electromagnetic engineering and science
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    • 제11권4호
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    • pp.304-310
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    • 2011
  • The application of time-domain methods in emission measurement instruments allows for a reduction in scan time by several orders of magnitude and for new evaluation methods to be realized such as the real-time spectrogram to characterize transient emissions. In this paper two novel systems for time-domain EMI measurements above 1 GHz are presented. The first system combines ultra-fast analog-to-digital-conversion and real-time digital signal processing on a field-programmable-gate-array (FPGA) with ultra-broadband multi-stage down-conversion to enable measurements in the range from 10 Hz to 26 GHz with high sensitivity and full-compliance with the requirements of CISPR 16-1-1. The required IF bandwidths were added to allow for measurements according to MIL-461F and DO-160F. The second system realizes a system of time-interleaved analog-to-digital converters (ADCs) and has an upper bandwidth limit of 4 GHz. With the implementation of an automatic mismatch calibration, the system fulfills CISPR 16-1-1 dynamic range requirements. Measurements of the radiated emissions of electronic consumer devices and household appliances like the non-stationary emissions of a microwave oven are presented. A measurement of a personal computer's conducted emissions on a power supply line according to DO-160F is given.

TMS320C6678을 적용한 소형 Radio Frequency 추적레이다용 고속 실시간 신호처리기 설계 (Development of High-Speed Real-Time Signal Processing Unit for Small Radio Frequency Tracking Radar Using TMS320C6678)

  • 김홍락;현효영;김윤진;우선걸;김광희
    • 한국인터넷방송통신학회논문지
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    • 제21권5호
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    • pp.11-18
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    • 2021
  • 소형 Radio Frequency 추적레이다는 표적에 대하여 전천후 Radio Frequency 신호 처리를 통하여 표적을 식별하고 주요 표적에 대하여 표적을 탐색, 탐지하여 추적하는 Radio Frequency 센서를 보유한 추적시스템이다. 본 논문에서는 전천후 Radio Frequency를 이용하여 표적 정보를 획득하여 실시간 신호처리를 통하여 표적을 식별하기 위한 고속의 멀티코어 DSP인 TMS320C6678과 XILINX FPGA(Field Programmable Gate Array)가 탑재된 보드 개발의 내용을 설명한다. DSP, FPGA 선정과 신호처리를 위한 DSP-FPGA 결합 아키텍처에 대하여 제안하고 또한 고속의 데이터 전송을 위한 SRIO의 설계에 대하여 설명한다.