The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
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Design of a 64b Multi-Time Programmable Memory IP for PMICs

PMIC용 저면적 64비트 MTP IP 설계

  • Cui, Dayong (Department of Electronic Engineering, Changwon National University) ;
  • Jin, Rijin (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Pang-Bong (Department of Electronic Engineering, Changwon National University) ;
  • Kim, Young-Hee (Department of Electronic Engineering, Changwon National University)
  • Received : 2016.06.27
  • Accepted : 2016.08.26
  • Published : 2016.08.30
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Abstract

In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.

본 논문에서는 저면적 64bit MTP IP를 설계하였다. 저면적 설계기술로는 MTP cell의 inhibit voltage를 기존의 VPP/3과 VNN/3 전압 대신 모두 0V를 사용하므로 VPPL(=VPP/3) regulator 회로와 VNNL(VNN/3) charge pump 회로를 제거하였다. 그리고 external pad를 이용하여 VPP program voltage를 forcing하므로 VPP charge pump 회로를 제거하였다. 또한 VNN charge pump는 VPP 전압을 이용하여 1-stage negative charge pump 회로로 pumping해서 -VPP의 전압을 공급하도록 설계를 하였다. 설계된 64bit MTP IP size는 $377.585{\mu}m{\times}328.265{\mu}m$(=0.124mm2)이며, DC-DC converter관련 layout size는 기존의 회로 대비 76.4%를 줄였다.

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References

  1. Hwang-Soo Chun, "Market Outlook and Domestic and Global Development Trend for Power Semiconductor," IITA Weekly Technology Trends, June 2009.
  2. Yining Yu et al., "Design of 256 bit Single-Poly MTP Memory Based on BCD Process," J. Cent. South Univ. Technol., vol. 19, no. 12, pp. 3460-3467, Dec. 2012. https://doi.org/10.1007/s11771-012-1430-6
  3. Yining Yu et al., "Design of 256 bit Single-Poly MTP Memory Based on BCD Process," J. Cent. South Univ. Technol., vol. 19, no. 12, pp. 3460-3467, Dec. 2012. https://doi.org/10.1007/s11771-012-1430-6
  4. F. Torricelli et al., "Half-MOS Based Single-Poly EEPROM Cell with Program and Erase Bit Granularity," IEEE Electron Device Letters, vol. 34, no. 12, Dec. 2013.
  5. Roizin, Yakov, et al., "High Density MTP Logic NVM for Power Management Applications," IEEE International Memory Workshop 2009, pp. 1-2, 2009.
  6. Yoon-Kyu Kim et al.," Design of Multi-Time- Programmable Memory for PMICs," ETRI Journal, pp. 1188-1198, Dec. 2015.