• 한국전기전자재료학회논문지
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• 제15권9호
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• pp.750-757
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• 2002

A new lateral trench LTEIGBT with p+ diverter was proposed to suppress latch-up of LTIGBT The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEICBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occured at an anode current density of 540A/$\textrm{cm}^2$. In addition, the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. The forward blocking voltage of the conventional LTIGBT of the same size was no more than 105V, We fabricated the proposed LTEIGBT with a p+ diverter after the device and process simulation was finished. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90㎃ and 70㎃, respectively, at the same breakdown voltage of 150V.

• 한국전기전자재료학회논문지
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• 제13권5호
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• pp.371-375
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• 2000

In this paper a new conductivity modulated power transistor called the Lateral Insulated Gated Bipolar Transistor which included n+ ring and p-channel gate is presented. A new lateral IGBT structure is proposed to suppress latch-up and to improve turn off time by imploying n+ ring and p-channel gate and verified by MEDICI. The simulated I-V characteristics at $V_{G}$=15V show that the latch up occurs at $V_{A}$=18V and 6.9$\times$10$^{-5}$ A/${\mu}{\textrm}{m}$ for the proposed LIGBT while the conventional LIGBT latches at $V_{A}$=1.3V and 1.96${\mu}{\textrm}{m}$10$^{-5A}$${\mu}{\textrm}{m}$. It is shown that turn off characteristic of new LIGBT is 8 times than that of conventional LIGBT. And noble LIGBT is not n+ buffer layer because that It includes p channel gate and n+ ring. Therefore Mask for the buffer layer isn’t needed. The concentration of n+ ring is and the numbers of n+ ring and p channel gate are three for the optimal design.n.n.n.n.

• Journal of Mechanical Science and Technology
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• 제20권12호
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• pp.2025-2033
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• 2006

This paper presents, the design of a latch mechanism for wafer containers in a standard mechanical interface environment. For an integrated circuits fabrication factory, the standard mechanical interfaced wafer container is an effective tool to prevent wafers from particle contamination during wafer storage, transporting or transferring. The latch mechanism inside the container door is used to latch and further seal the wafer container for safety and air quality. Kinematic characteristics of the mechanism are established by analyzing the required functions of the mechanisms. Based on these characteristics, a methodology for enumerating feasible latch mechanisms is developed. New mechanisms with one degree-of-freedom and up to five links are generated. An optimum design is also identified with respect to the criteria pertinent to the application. The computer-aided simulation is also built to verify the design.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2003년도 춘계학술대회논문집
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• pp.1157-1164
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• 2003

Dynamic Load/unload (L/UL) mechanism is an alternative to the contact start stop (CSS) technology which eliminates stiction and wear failure modes associated with CSS. Other benefits of L/UL include increased areal density due to smooth disk surfaces, thinner overcoats, and lower head flying height Improved shock resistance due to elimination of head slap, and reduced power consumption. Inertia latch mechanism becomes important for mobile disk drives because of non operating shock performance. Various types of latch designs have been introduced in hard disk drives to limit a rotary actuator from sudden uncontrolled motion. In this paper, a single spring inertia latch is introduced for a small form optical disk drive, which uses a rotary actuator for moving an optical pick-up. A new small inertia latch with single spring is designed to ensure both feasible and small size. The shock performance of the new inertia latch is experimentally verified.

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.912-917
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• 2006

In this paper, Trench emitter electrode IGBT structure is proposed and studied numerically using the device simulator, MEDICI. The breakdown voltage, on-state voltage drop, latch up current density and turn-off time of the proposed structure are compared with those of the conventional trench gate IGBT(TIGBT) structures. Enhancement of the breakdown voltage by 19 % is obtained in the proposed structure due to dispersion of electric field at the edge of the bottom trench gate by trench emitter electrode. In addition, the on-state voltage drop and the latch up current density are improved by 25 %, 16 % respectively. However increase of turn-off time in proposed structures are negligible.

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.21-25
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• 2007

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.63-66
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• 2005

A soft error rate neutrons is a growing problem for integrated circuits with technology scaling. In the acceleration test with high-density neutron beam, a latch-up prohibits accurate estimations of the soft error rate (SER). This paper presents results of analysis for the latch-up characteristics in the circumstance corresponding to the acceleration SER test for SRAM. Simulation results, using a two-dimensional device simulator, show that the deep p-well structure has better latch-up Immunity compared to normal twin and triple well structures. In addition, it is more effective to minimize the distance to ground power compared with controlling a path to the $V_{DD}$ power.

• 전기전자학회논문지
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• 제26권2호
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• pp.196-204
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• 2022

Electrostatic discharge (ESD) protection devices of P-type embedded silicon-controlled rectifier (PESCR) structure were analyzed for high-voltage operating input/output (I/O) applications. Conventional PESCR standard device exhibits typical SCR characteristics with very low-snapback holding voltages, resulting in latch-up problems during normal operation. However, the modified device with the counter pocket source (CPS) surrounding N⁺ source region and partially formed P-well (PPW) structures proposed in this study could improve latch-up immunity by indicating high on-resistance and snapback holding voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• 한국산업융합학회 논문집
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• 제5권1호
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.