• 전자공학회논문지D
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• 제35D권11호
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• pp.62-69
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• 1998

Hot carrier 스트레스후의 RF-nMOSFET의 DC 및 RF 특성열화를 분석하기 위해 기존의 열화 모델을 적용하였다. 드레인전류 열화보다 차단주파수 열화가 심하였으며 RF-nMOSFET의 열화변화율 n과 열화변수 m은 기존의 bulk MOSFET의 것과 같았다. Multi-finger 게이트 소자에서 finger수가 많을수록 열화가 적게 된 것은 큰 소스/드레인의 저항과 포화전압에 의한 것임을 알 수 있었다. 스트레스의 후의 RF성능 저하는 g/sub m/과 C/sub gd/의 감소와 g/sub ds/의 증가에 의한 것임을 알 수 있었다. 기판전류를 측정하므로 RF소자의 DC 및 RF특성 열화를 예견할 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.40-40
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• 2009

The electrical characteristic of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects such as large leakage current, kink effect and hot-carrier effects. In this paper, LTPS TFTs with different GOLDD length were fabricated and investigated the effect of the GOLDD. GOLDD length of 1, 1.5 and $2{\mu}m$ were used, while the thickness of the gate dielectrics($SiN_x/SiO_2$) was fixed at 65nm(40nm/25nm). The electrical characteristics show that the kink effect is reduced at the LTPS TFTs, and degradation from the hot-carrier effect was also decreased by increasing GOLDD length.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.191-197
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• 2016

In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.216.2-216.2
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• 2015

본 연구에서는 charge pumping method에서 사용되는 변수들의 변화를 이용하여 hot carrier stress가 MOSFET소자의 oxide내에서의 trap 분포에 어떤 영향을 미치는지에 대해서 연구하였다. trap 분포를 확인하기 위해 스트레스 전 후에 reverse bias와 주파수에 따른 trap의 양을 측정 하였다. 스트레스 전과 후에 reverse bias와 주파수가 감소할수록 trap이 증가하는 모습이 나타났고, 스트레스 후에는 전과 비교하여 전반적으로 trap의 양이 증가하였다. 또한, 스트레스 전과 후에 MOSFET소자의 trap density는 center region에서 $2.89{\times}$10^10에서 $1.64{\times}$10^10으로 감소하였고, drain region에서 $2.83{\times}$10^10에서 $5.26{\times}$10^10으로 증가한 것을 확인하였다. 이는 reverse bias와 주파수의 가변에 따라서 trap의 공간적 분포를 측정할 수 있다는 것을 의미한다.

• 전자공학회논문지A
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• 제30A권8호
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• pp.49-56
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• 1993

In this paper, we present a new lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and substrate current influence. The suggested model is applied to a different channel structured PMOSFET, dgm/gm of both SC-PMOSFET and BC-PMOSFET appear with one straigth line about Qbib, therefore, this model is independent of channel structure. The suggested model is applied to a different drain structured SC-PMOSFET. Unlike S/D structured SC-PMOSFET, dgm/gm of LDD structured SC-PMOSFET appears with one straight line about Qb, therefore, this model is dependent of drain structure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• 한국결정성장학회지
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• 제14권2호
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1327-1329
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• 1998

It is very important to select superior inter-layer PMD(Pre Metal Dielectric) materials which can act as penetration barrier to various impurities created by CMP processes. In this paper, hot carrier degradation and device characteristics were studied with material variation of PMD-1 layers, which were split by LP-TEOS, SR-Oxide, PE-Oxynitride, PE-Nitride, PE-TEOS films. It was observed that the oxynitride and nitride using plasma was greatly decreased in hot carrier effect in comparison with silicon oxide. Consequently, silicon oxide turned out to be a better PMD-1 material than PE-oxynitride and PE-nitride. Also, LP-TEOS film was the best PMD-1 material Among the silicon oxides.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1105-1108
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• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.